ARMJIT: disable vi2f, it seems buggy. preliminary disabled impl of vcrsp.t.

Common/x64Emitter.h

@@ -112,6 +112,18 @@ enum NormalOp {
 	nrmXCHG,
 };
 
+enum
+{
+	CMP_EQ = 0,
+	CMP_LT = 1,
+	CMP_LE = 2,
+	CMP_UNORD = 3,
+	CMP_NEQ = 4,
+	CMP_NLT = 5,
+	CMP_NLE = 6,
+	CMP_ORD = 7,
+};
+
 class XEmitter;
 
 // RIP addressing does not benefit from micro op fusion on Core arch
@@ -231,18 +243,6 @@ struct FixupBranch
 	int type; //0 = 8bit 1 = 32bit
 };
 
-enum SSECompare
-{
-	EQ = 0,
-	LT,
-	LE,
-	UNORD,
-	NEQ,
-	NLT,
-	NLE,
-	ORD,
-};
-
 typedef const u8* JumpTarget;
 
 class XEmitter
@@ -468,6 +468,15 @@ public:
 	void CMPSS(X64Reg regOp, OpArg arg, u8 compare);  
 	void CMPSD(X64Reg regOp, OpArg arg, u8 compare);  
 
+	inline void CMPEQSS(X64Reg regOp, OpArg arg) { CMPSS(regOp, arg, CMP_EQ); }
+	inline void CMPLTSS(X64Reg regOp, OpArg arg) { CMPSS(regOp, arg, CMP_LT); }
+	inline void CMPLESS(X64Reg regOp, OpArg arg) { CMPSS(regOp, arg, CMP_LE); }
+	inline void CMPUNORDSS(X64Reg regOp, OpArg arg) { CMPSS(regOp, arg, CMP_UNORD); }
+	inline void CMPNEQSS(X64Reg regOp, OpArg arg) { CMPSS(regOp, arg, CMP_NEQ); }
+	inline void CMPNLTSS(X64Reg regOp, OpArg arg) { CMPSS(regOp, arg, CMP_NLT); }
+	inline void CMPORDSS(X64Reg regOp, OpArg arg) { CMPSS(regOp, arg, CMP_ORD); }
+
+
 	// I don't think these exist
 	/*
 	void ANDSD(X64Reg regOp, OpArg arg);  

Core/MIPS/ARM/ArmCompVFPU.cpp

@@ -29,6 +29,8 @@
 #include "ArmRegCache.h"
 
 
+const bool disablePrefixes = false;
+
 // All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.
 // Currently known non working ones should have DISABLE.
 
@@ -78,7 +80,6 @@ namespace MIPSComp
 		int regnum = (op >> 24) & 3;
 		switch (regnum) {
 		case 0:  // S
-			//ERROR_LOG(CPU, "VPFX - S %08x %i", data, regnum);
 			js.prefixS = data;
 			js.prefixSFlag = ArmJitState::PREFIX_KNOWN_DIRTY;
 			break;
@@ -437,7 +438,7 @@ namespace MIPSComp
 		CONDITIONAL_DISABLE;
 
 		// WARNING: No prefix support!
-		if (js.HasUnknownPrefix()) {
+		if (js.HasUnknownPrefix() || disablePrefixes) {
 			DISABLE;
 		}
 
@@ -472,7 +473,7 @@ namespace MIPSComp
 	void Jit::Comp_VIdt(u32 op) {
 		CONDITIONAL_DISABLE
 
-		if (js.HasUnknownPrefix()) {
+		if (js.HasUnknownPrefix() || disablePrefixes) {
 			DISABLE;
 		}
 
@@ -510,7 +511,7 @@ namespace MIPSComp
 	{
 		CONDITIONAL_DISABLE;
 
-		if (js.HasUnknownPrefix()) {
+		if (js.HasUnknownPrefix() || disablePrefixes) {
 			DISABLE;
 		}
 
@@ -554,10 +555,9 @@ namespace MIPSComp
 		fpr.ReleaseSpillLocksAndDiscardTemps();
 	}
 
-	void Jit::Comp_VDot(u32 op)
+	void Jit::Comp_VDot(u32 op) {
-	{
 		CONDITIONAL_DISABLE;
-		if (js.HasUnknownPrefix()) {
+		if (js.HasUnknownPrefix() || disablePrefixes) {
 			DISABLE;
 		}
 
@@ -567,9 +567,10 @@ namespace MIPSComp
 		VectorSize sz = GetVecSize(op);
 
 		// TODO: Force read one of them into regs? probably not.
-		u8 sregs[4], tregs[4];
+		u8 sregs[4], tregs[4], dregs[1];
-		GetVectorRegs(sregs, sz, vs);
+		GetVectorRegsPrefixS(sregs, sz, vs);
-		GetVectorRegs(tregs, sz, vt);
+		GetVectorRegsPrefixT(tregs, sz, vt);
+		GetVectorRegsPrefixD(dregs, V_Single, vd);
 
 		// TODO: applyprefixST here somehow (shuffle, etc...)
 		fpr.MapRegsAndSpillLockV(sregs, sz, 0);
@@ -583,19 +584,24 @@ namespace MIPSComp
 		}
 		fpr.ReleaseSpillLocksAndDiscardTemps();
 
-		fpr.MapRegV(vd, MAP_NOINIT | MAP_DIRTY);
+		fpr.MapRegV(dregs[0], MAP_NOINIT | MAP_DIRTY);
 
 		// TODO: applyprefixD here somehow (write mask etc..)
-		VMOV(fpr.V(vd), S0);
+		VMOV(fpr.V(dregs[0]), S0);
+		ApplyPrefixD(dregs, V_Single);
+		fpr.ReleaseSpillLocksAndDiscardTemps();
 	}
 
+	void Jit::Comp_VHdp(u32 op) {
+		// Similar to vdot
+		DISABLE;
+	}
+
+
 	void Jit::Comp_VecDo3(u32 op) {
 		CONDITIONAL_DISABLE;
 		
-		// WARNING: No prefix support!
+		if (js.HasUnknownPrefix() || disablePrefixes) {
-
-		//if (js.MayHavePrefix()) {
-		if (js.HasUnknownPrefix()) {
 			DISABLE;
 		}
 
@@ -671,7 +677,7 @@ namespace MIPSComp
 	void Jit::Comp_VV2Op(u32 op) {
 		CONDITIONAL_DISABLE;
 
-		if (js.HasUnknownPrefix()) {
+		if (js.HasUnknownPrefix() || disablePrefixes) {
 			DISABLE;
 		}
 
@@ -796,8 +802,9 @@ namespace MIPSComp
 
 	void Jit::Comp_Vi2f(u32 op) {
 		CONDITIONAL_DISABLE;
+		DISABLE;
 
-		if (js.HasUnknownPrefix())
+		if (js.HasUnknownPrefix() || disablePrefixes)
 			DISABLE;
 
 		VectorSize sz = GetVecSize(op);
@@ -840,8 +847,6 @@ namespace MIPSComp
 		fpr.ReleaseSpillLocksAndDiscardTemps();
 	}
 
-
-
 	void Jit::Comp_Mftv(u32 op)
 	{
 		CONDITIONAL_DISABLE;
@@ -968,7 +973,7 @@ namespace MIPSComp
 	void Jit::Comp_VScl(u32 op) {
 		CONDITIONAL_DISABLE;
 
-		if (js.HasUnknownPrefix()) {
+		if (js.HasUnknownPrefix() || disablePrefixes) {
 			DISABLE;
 		}
 
@@ -1018,7 +1023,7 @@ namespace MIPSComp
 		CONDITIONAL_DISABLE;
 
 		// TODO: This probably ignores prefixes?
-		if (js.MayHavePrefix()) {
+		if (js.MayHavePrefix() || disablePrefixes) {
 			DISABLE;
 		}
 
@@ -1064,8 +1069,9 @@ namespace MIPSComp
 		CONDITIONAL_DISABLE;
 
 		// TODO: This probably ignores prefixes?  Or maybe uses D?
-		if (js.MayHavePrefix())
+		if (js.MayHavePrefix() || disablePrefixes) {
 			DISABLE;
+		}
 
 		VectorSize sz = GetVecSize(op);
 		MatrixSize msz = GetMtxSize(op);
@@ -1073,8 +1079,7 @@ namespace MIPSComp
 		int ins = (op >> 23) & 7;
 
 		bool homogenous = false;
-		if (n == ins)
+		if (n == ins) {
-		{
 			n++;
 			sz = (VectorSize)((int)(sz) + 1);
 			msz = (MatrixSize)((int)(msz) + 1);
@@ -1120,10 +1125,6 @@ namespace MIPSComp
 		fpr.ReleaseSpillLocksAndDiscardTemps();
 	}
 
-	void Jit::Comp_VHdp(u32 op) {
-		DISABLE;
-	}
-
 	void Jit::Comp_VCrs(u32 op) {
 		DISABLE;
 	}
@@ -1146,10 +1147,56 @@ namespace MIPSComp
 
 	void Jit::Comp_VCrossQuat(u32 op) {
 		DISABLE;
+
+		// This op does not support prefixes.
+		if (js.HasUnknownPrefix() || disablePrefixes)
+			DISABLE;
+
+		VectorSize sz = GetVecSize(op);
+		int n = GetNumVectorElements(sz);
+
+		u8 sregs[4], tregs[4], dregs[4];
+		GetVectorRegs(sregs, sz, _VS);
+		GetVectorRegs(tregs, sz, _VT);
+		GetVectorRegs(dregs, sz, _VD);
+
+		// Map everything into registers.
+		fpr.MapRegsAndSpillLockV(sregs, sz, 0);
+		fpr.MapRegsAndSpillLockV(tregs, sz, 0);
+
+		if (sz == V_Triple) {
+			int temp3 = fpr.GetTempV();
+			fpr.MapRegV(temp3, MAP_DIRTY | MAP_NOINIT);
+			// Cross product vcrsp.t
+
+			// Compute X
+			VMUL(S0, fpr.V(sregs[1]), fpr.V(tregs[2]));
+			VMLS(S0, fpr.V(sregs[2]), fpr.V(tregs[1]));
+
+			// Compute Y
+			VMUL(S1, fpr.V(sregs[2]), fpr.V(tregs[0]));
+			VMLS(S1, fpr.V(sregs[0]), fpr.V(tregs[2]));
+
+			// Compute Z
+			VMUL(fpr.V(temp3), fpr.V(sregs[2]), fpr.V(tregs[0]));
+			VMLS(fpr.V(temp3), fpr.V(sregs[0]), fpr.V(tregs[2]));
+
+			fpr.MapRegsAndSpillLockV(dregs, V_Triple, MAP_DIRTY | MAP_NOINIT);
+			VMOV(fpr.V(dregs[0]), S0);
+			VMOV(fpr.V(dregs[1]), S1);
+			VMOV(fpr.V(dregs[2]), fpr.V(temp3));
+		} else if (sz == V_Quad) {
+			// Quaternion product  vqmul.q  untested
+			DISABLE;
+		}
+
+		fpr.ReleaseSpillLocksAndDiscardTemps();
 	}
 
 	void Jit::Comp_Vsge(u32 op) {
 		DISABLE;
+
+
 	}
 
 	void Jit::Comp_Vslt(u32 op) {
@@ -1160,7 +1207,7 @@ namespace MIPSComp
 		// Not ready yet
 		DISABLE;
 
-		if (js.HasUnknownPrefix())
+		if (js.HasUnknownPrefix() || disablePrefixes)
 			DISABLE;
 
 		VectorSize sz = GetVecSize(op);
@@ -1312,7 +1359,7 @@ namespace MIPSComp
 	void Jit::Comp_Vfim(u32 op) {
 		CONDITIONAL_DISABLE;
 
-		if (js.HasUnknownPrefix()) {
+		if (js.HasUnknownPrefix() || disablePrefixes) {
 			DISABLE;
 		}
 
@@ -1332,7 +1379,7 @@ namespace MIPSComp
 	void Jit::Comp_Vcst(u32 op) {
 		CONDITIONAL_DISABLE;
 
-		if (js.HasUnknownPrefix()) {
+		if (js.HasUnknownPrefix() || disablePrefixes) {
 			DISABLE;
 		}
 
@@ -1390,7 +1437,7 @@ namespace MIPSComp
 		CONDITIONAL_DISABLE;
 		
 		// This op doesn't support prefixes anyway..
-		if (js.HasUnknownPrefix()) {
+		if (js.HasUnknownPrefix() || disablePrefixes) {
 			DISABLE;
 		}
 

Core/MIPS/ARM/ArmRegCacheFPU.cpp

@@ -45,7 +45,7 @@ void ArmRegCacheFPU::Start(MIPSAnalyst::AnalysisResults &stats) {
 }
 
 static const ARMReg *GetMIPSAllocationOrder(int &count) {
-	// We conservatively reserve both S0 and S1 as scratch for now.
+	// We conservatively reserve both S0-S2 as scratch for now.
 	static const ARMReg allocationOrder[] = {
 		S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15
 	};

Core/MIPS/x86/CompFPU.cpp

@@ -153,18 +153,6 @@ static const u64 GC_ALIGNED16(ssNoSignMask[2]) = {0x7FFFFFFF7FFFFFFFULL, 0x7FFFF
 
 static u32 ssCompareTemp;
 
-enum
-{
-	CMPEQSS = 0,
-	CMPLTSS = 1,
-	CMPLESS = 2,
-	CMPUNORDSS = 3,
-	CMPNEQSS = 4,
-	CMPNLTSS = 5,
-	CMPNLESS = 6,
-	CMPORDSS = 7,
-};
-
 void Jit::CompFPComp(int lhs, int rhs, u8 compare, bool allowNaN)
 {
 	MOVSS(XMM0, fpr.R(lhs));
@@ -175,7 +163,7 @@ void Jit::CompFPComp(int lhs, int rhs, u8 compare, bool allowNaN)
 	if (allowNaN)
 	{
 		MOVSS(XMM0, fpr.R(lhs));
-		CMPSS(XMM0, fpr.R(rhs), CMPUNORDSS);
+		CMPUNORDSS(XMM0, fpr.R(rhs));
 		MOVSS(M((void *) &ssCompareTemp), XMM0);
 
 		MOV(32, R(EAX), M((void *) &ssCompareTemp));
@@ -199,37 +187,37 @@ void Jit::Comp_FPUComp(u32 op)
 
 	case 1: //un
 	case 9: //ngle
-		CompFPComp(fs, ft, CMPUNORDSS);
+		CompFPComp(fs, ft, CMP_UNORD);
 		break;
 
 	case 2: //eq
 	case 10: //seq
-		CompFPComp(fs, ft, CMPEQSS);
+		CompFPComp(fs, ft, CMP_EQ);
 		break;
 
 	case 3: //ueq
 	case 11: //ngl
-		CompFPComp(fs, ft, CMPEQSS, true);
+		CompFPComp(fs, ft, CMP_EQ, true);
 		break;
 
 	case 4: //olt
 	case 12: //lt
-		CompFPComp(fs, ft, CMPLTSS);
+		CompFPComp(fs, ft, CMP_LT);
 		break;
 
 	case 5: //ult
 	case 13: //nge
-		CompFPComp(ft, fs, CMPNLESS);
+		CompFPComp(ft, fs, CMP_NLE);
 		break;
 
 	case 6: //ole
 	case 14: //le
-		CompFPComp(fs, ft, CMPLESS);
+		CompFPComp(fs, ft, CMP_LE);
 		break;
 
 	case 7: //ule
 	case 15: //ngt
-		CompFPComp(ft, fs, CMPNLTSS);
+		CompFPComp(ft, fs, CMP_NLT);
 		break;
 
 	default:

Core/MIPS/x86/CompVFPU.cpp

@@ -708,18 +708,6 @@ void Jit::Comp_VecDo3(u32 op) {
 	fpr.ReleaseSpillLocks();
 }
 
-enum
-{
-	CMPEQSS = 0,
-	CMPLTSS = 1,
-	CMPLESS = 2,
-	CMPUNORDSS = 3,
-	CMPNEQSS = 4,
-	CMPNLTSS = 5,
-	CMPNLESS = 6,
-	CMPORDSS = 7,
-};
-
 static float ssCompareTemp;
 
 void Jit::Comp_Vcmp(u32 op) {
@@ -772,44 +760,44 @@ void Jit::Comp_Vcmp(u32 op) {
 			break;
 
 		case VC_EQ: // c = s[i] == t[i]; break;
-			comparison = CMPEQSS;
+			comparison = CMP_EQ;
 			compareTwo = true;
 			break;
 
 		case VC_LT: // c = s[i] < t[i]; break;
-			comparison = CMPLTSS;
+			comparison = CMP_LT;
 			compareTwo = true;
 			break;
 
 		case VC_LE: // c = s[i] <= t[i]; break;
-			comparison = CMPLESS;
+			comparison = CMP_LE;
 			compareTwo = true;
 			break;
 
 		case VC_NE: // c = s[i] != t[i]; break;
-			comparison = CMPNEQSS;
+			comparison = CMP_NEQ;
 			compareTwo = true;
 			break;
 
 		case VC_GE: // c = s[i] >= t[i]; break;
-			comparison = CMPLESS;
+			comparison = CMP_LE;
 			flip = true;
 			compareTwo = true;
 			break;
 
 		case VC_GT: // c = s[i] > t[i]; break;
-			comparison = CMPLTSS;
+			comparison = CMP_LT;
 			flip = true;
 			compareTwo = true;
 			break;
 
 		case VC_EZ: // c = s[i] == 0.0f || s[i] == -0.0f; break;
-			comparison = CMPEQSS;
+			comparison = CMP_EQ;
 			compareToZero = true;
 			break;
 
 		case VC_NZ: // c = s[i] != 0; break;
-			comparison = CMPNEQSS;
+			comparison = CMP_NEQ;
 			compareToZero = true;
 			break;
 
@@ -869,6 +857,14 @@ void Jit::Comp_Vcmp(u32 op) {
 	gpr.UnlockAllX();
 }
 
+void Jit::Comp_Vsge(u32 op) {
+	DISABLE;
+}
+
+void Jit::Comp_Vslt(u32 op) {
+	DISABLE;
+}
+
 // There are no immediates for floating point, so we need to load these
 // from RAM. Might as well have a table ready.
 extern const float mulTableVi2f[32] = {
@@ -1466,14 +1462,6 @@ void Jit::Comp_Vcmov(u32 op) {
 	DISABLE;
 }
 
-void Jit::Comp_Vsge(u32 op) {
-	DISABLE;
-}
-
-void Jit::Comp_Vslt(u32 op) {
-	DISABLE;
-}
-
 void Jit::Comp_Viim(u32 op) {
 	CONDITIONAL_DISABLE;
 

UI/EmuScreen.cpp

@@ -322,7 +322,7 @@ void EmuScreen::pspKey(int pspKeyCode, int flags) {
 			onVKeyUp(pspKeyCode);
 		}
 	} else {
-		ILOG("pspKey %i %i", pspKeyCode, flags);
+		// ILOG("pspKey %i %i", pspKeyCode, flags);
 		if (flags & KEY_DOWN)
 			__CtrlButtonDown(pspKeyCode);
 		if (flags & KEY_UP)

native

@@ -1 +1 @@
-Subproject commit 14833656898f4c711201d95446228f51722cf0cc
+Subproject commit f00bfc546401e93803f1b41ba64804247b8ac6c7