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Improve an assert message that AkiraJkr saw. Fix a silly bug in the last commit.

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Henrik Rydgård 2019-08-23 18:40:13 +02:00
parent 7196d6ac7e
commit 31de5a5082
1 changed files with 4 additions and 4 deletions
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8
Core/MIPS/x86/RegCacheFPU.h
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@ -126,11 +126,11 @@ public:
const Gen::OpArg &R(int freg) const {return regs[freg].location;}
const Gen::OpArg &V(int vreg) const {
_dbg_assert_msg_(JIT, vregs[vreg].lane == 0, "SIMD reg %d used as V reg (use VS instead)", vreg);
_dbg_assert_msg_(JIT, vregs[vreg].lane == 0, "SIMD reg %d used as V reg (use VS instead). pc=%08x", vreg, mips->pc);
return vregs[vreg].location;
}
const Gen::OpArg &VS(const u8 *vs) const {
_dbg_assert_msg_(JIT, vregs[vs[0]].lane != 0, "V reg %d used as VS reg (use V instead)", vs[0]);
_dbg_assert_msg_(JIT, vregs[vs[0]].lane != 0, "V reg %d used as VS reg (use V instead). pc=%08x", vs[0], mips->pc);
return vregs[vs[0]].location;
}
@ -142,7 +142,7 @@ public:
}
Gen::X64Reg VX(int vreg) const {
_dbg_assert_msg_(JIT, vregs[vreg].lane == 0, "SIMD reg %d used as V reg (use VSX instead)", vreg);
_dbg_assert_msg_(JIT, vregs[vreg].lane == 0, "SIMD reg %d used as V reg (use VSX instead). pc=%08x", vreg, mips->pc);
if (vregs[vreg].away && vregs[vreg].location.IsSimpleReg())
return vregs[vreg].location.GetSimpleReg();
PanicAlert("Not so simple - v%i", vreg);
@ -150,7 +150,7 @@ public:
}
Gen::X64Reg VSX(const u8 *vs) const {
_dbg_assert_msg_(JIT, vregs[vs[0]].lane != 0, "V reg %d used as VS reg (use VX instead)", vs[0]);
_dbg_assert_msg_(JIT, vregs[vs[0]].lane != 0, "V reg %d used as VS reg (use VX instead). pc=%08x", vs[0], mips->pc);
if (vregs[vs[0]].away && vregs[vs[0]].location.IsSimpleReg())
return vregs[vs[0]].location.GetSimpleReg();
PanicAlert("Not so simple - v%i", vs[0]);