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ARM: Some zero-register fixes

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This commit is contained in:
Henrik Rydgard 2013-11-07 13:38:25 +01:00
parent 91393093bc
commit 32c95af820
3 changed files with 18 additions and 15 deletions
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2
Core/MIPS/ARM/ArmCompALU.cpp
View File

@ -55,7 +55,7 @@ namespace MIPSComp
gpr.SetImm(rt, (*eval)(gpr.GetImm(rs), uimm));
} else {
gpr.MapDirtyIn(rt, rs);
// TODO: Special case when uimm can be represented as an Operand2
// Special case when uimm can be represented as an Operand2
Operand2 op2;
if (TryMakeOperand2(uimm, op2)) {
(this->*arith)(gpr.R(rt), gpr.R(rs), op2);

3
Core/MIPS/ARM/ArmCompLoadStore.cpp
View File

@ -142,8 +142,7 @@ namespace MIPSComp
u32 iaddr = gpr.IsImm(rs) ? offset + gpr.GetImm(rs) : 0xFFFFFFFF;
bool doCheck = false;
switch (o)
{
switch (o) {
case 32: //lb
case 33: //lh
case 35: //lw

28
Core/MIPS/ARM/ArmRegCache.cpp
View File

@ -103,17 +103,17 @@ allocate:
// That means it's free. Grab it, and load the value into it (if requested).
ar[reg].isDirty = (mapFlags & MAP_DIRTY) ? true : false;
if (!(mapFlags & MAP_NOINIT)) {
if (mr[mipsReg].loc == ML_MEM) {
if (mipsReg != 0) {
if (mipsReg == 0) {
// If we get a request to load the zero register, at least we won't spend
// time on a memory access...
emit_->MOV((ARMReg)reg, 0);
} else {
if (mr[mipsReg].loc == ML_MEM) {
emit_->LDR((ARMReg)reg, CTXREG, GetMipsRegOffset(mipsReg));
} else {
// If we get a request to load the zero register, at least we won't spend
// time on a memory access...
emit_->MOV((ARMReg)reg, 0);
} else if (mr[mipsReg].loc == ML_IMM) {
emit_->MOVI2R((ARMReg)reg, mr[mipsReg].imm);
ar[reg].isDirty = true; // IMM is always dirty.
}
} else if (mr[mipsReg].loc == ML_IMM) {
emit_->MOVI2R((ARMReg)reg, mr[mipsReg].imm);
ar[reg].isDirty = true; // IMM is always dirty.
}
}
ar[reg].mipsReg = mipsReg;
@ -204,8 +204,10 @@ void ArmRegCache::FlushR(MIPSReg r) {
switch (mr[r].loc) {
case ML_IMM:
// IMM is always "dirty".
emit_->MOVI2R(R0, mr[r].imm);
emit_->STR(R0, CTXREG, GetMipsRegOffset(r));
if (r != 0) {
emit_->MOVI2R(R0, mr[r].imm);
emit_->STR(R0, CTXREG, GetMipsRegOffset(r));
}
break;
case ML_ARMREG:
@ -213,7 +215,9 @@ void ArmRegCache::FlushR(MIPSReg r) {
ERROR_LOG(JIT, "FlushMipsReg: MipsReg had bad ArmReg");
}
if (ar[mr[r].reg].isDirty) {
emit_->STR((ARMReg)mr[r].reg, CTXREG, GetMipsRegOffset(r));
if (r != 0) {
emit_->STR((ARMReg)mr[r].reg, CTXREG, GetMipsRegOffset(r));
}
ar[mr[r].reg].isDirty = false;
}
ar[mr[r].reg].mipsReg = -1;