From 3303a71796374155918b0dbe22cd8c3414f91a29 Mon Sep 17 00:00:00 2001
From: Henrik Rydgard <hrydgard@gmail.com>
Date: Wed, 31 Jul 2013 11:25:35 +0200
Subject: [PATCH] Oops

---
 Core/MIPS/ARM/ArmCompVFPU.cpp    | 4 ++++
 Core/MIPS/ARM/ArmRegCacheFPU.cpp | 2 +-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/Core/MIPS/ARM/ArmCompVFPU.cpp b/Core/MIPS/ARM/ArmCompVFPU.cpp
index ba75bfb396..e935020e99 100644
--- a/Core/MIPS/ARM/ArmCompVFPU.cpp
+++ b/Core/MIPS/ARM/ArmCompVFPU.cpp
@@ -185,10 +185,12 @@ namespace MIPSComp
 				MOVI2F(S0, 0.0f, R0);
 				MOVI2F(S1, 1.0f, R0);
 				VCMP(fpr.V(vregs[i]), S0);
+				VMRS_APSR(); // Move FP flags from FPSCR to APSR (regular flags).
 				SetCC(CC_LE);
 				VMOV(fpr.V(vregs[i]), S0);
 				SetCC(CC_AL);
 				VCMP(fpr.V(vregs[i]), S1);
+				VMRS_APSR(); // Move FP flags from FPSCR to APSR (regular flags).
 				SetCC(CC_GT);
 				VMOV(fpr.V(vregs[i]), S1);
 				SetCC(CC_AL);
@@ -205,10 +207,12 @@ namespace MIPSComp
 				MOVI2F(S0, -1.0f, R0);
 				MOVI2F(S1, 1.0f, R0);
 				VCMP(fpr.V(vregs[i]), S0);
+				VMRS_APSR(); // Move FP flags from FPSCR to APSR (regular flags).
 				SetCC(CC_LT);
 				VMOV(fpr.V(vregs[i]), S0);
 				SetCC(CC_AL);
 				VCMP(fpr.V(vregs[i]), S1);
+				VMRS_APSR(); // Move FP flags from FPSCR to APSR (regular flags).
 				SetCC(CC_GT);
 				VMOV(fpr.V(vregs[i]), S1);
 				SetCC(CC_AL);
diff --git a/Core/MIPS/ARM/ArmRegCacheFPU.cpp b/Core/MIPS/ARM/ArmRegCacheFPU.cpp
index c4e9f3fd14..772eeb4f28 100644
--- a/Core/MIPS/ARM/ArmRegCacheFPU.cpp
+++ b/Core/MIPS/ARM/ArmRegCacheFPU.cpp
@@ -370,7 +370,7 @@ void ArmRegCacheFPU::ReleaseSpillLocksAndDiscardTemps() {
 		DiscardR(i);
 }
 
-ARMReg ArmRegCacheFPU::R(int mi psReg) {
+ARMReg ArmRegCacheFPU::R(int mipsReg) {
 	if (mr[mipsReg].loc == ML_ARMREG) {
 		return (ARMReg)(mr[mipsReg].reg + S0);
 	} else {