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Merge pull request #4467 from unknownbrackets/perf
Avoid literal loads in the arm vertexjit.
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commit
340359fa84
@ -996,7 +996,7 @@ void VertexDecoderJitCache::Jit_Color565() {
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// Expand 5 -> 8.
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LSL(tempReg3, tempReg2, 3);
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ORR(tempReg2, tempReg3, Operand2(tempReg2, ST_LSR, 2));
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ANDI2R(tempReg2, tempReg2, 0x00FF00FF, scratchReg);
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ANDI2R(tempReg2, tempReg2, 0xFFFF00FF, scratchReg);
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// Now finally G. We start by shoving it into a wall.
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LSR(tempReg1, tempReg1, 5);
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@ -1024,7 +1024,8 @@ void VertexDecoderJitCache::Jit_Color5551() {
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// Expand 5 -> 8.
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LSR(tempReg3, tempReg2, 2);
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// Clean up the bits that were shifted right.
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ANDI2R(tempReg3, tempReg1, 0x07070707, scratchReg);
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BIC(tempReg3, tempReg1, AssumeMakeOperand2(0x000000F8));
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BIC(tempReg3, tempReg3, AssumeMakeOperand2(0x0000F800));
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ORR(tempReg2, tempReg3, Operand2(tempReg2, ST_LSL, 3));
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// Now we just need alpha.
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