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https://github.com/hrydgard/ppsspp.git
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MIPSTables: Annotate fp and hi/lo in/out more accurately than just "other"
Some typo fixes
This commit is contained in:
Henrik Rydgård
Henrik Rydgard
parent
281ab5f9cb
commit
3b1476c8ec
@ -772,7 +772,7 @@ bool DisassemblyMacro::disassemble(u32 address, DisassemblyLineInfo& dest, bool
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dest.params = buffer;
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dest.info.hasRelevantAddress = true;
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dest.info.releventAddress = immediate;
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dest.info.relevantAddress = immediate;
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break;
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case MACRO_MEMORYIMM:
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dest.name = name;
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@ -792,7 +792,7 @@ bool DisassemblyMacro::disassemble(u32 address, DisassemblyLineInfo& dest, bool
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dest.info.dataSize = dataSize;
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dest.info.hasRelevantAddress = true;
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dest.info.releventAddress = immediate;
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dest.info.relevantAddress = immediate;
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break;
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default:
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return false;
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@ -26,8 +26,7 @@ class PointerWrap;
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typedef Memory::Opcode MIPSOpcode;
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enum MIPSGPReg
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{
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enum MIPSGPReg {
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MIPS_REG_ZERO=0,
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MIPS_REG_COMPILER_SCRATCH=1,
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@ -65,17 +64,16 @@ enum MIPSGPReg
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MIPS_REG_FP=30,
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MIPS_REG_RA=31,
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MIPS_REG_INVALID=-1,
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// Not real regs, just for convenience/jit mapping.
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MIPS_REG_HI = 32,
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MIPS_REG_LO = 33,
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MIPS_REG_FPCOND = 34,
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MIPS_REG_VFPUCC = 35,
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MIPS_REG_INVALID=-1,
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};
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enum
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{
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enum {
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VFPU_CTRL_SPREFIX,
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VFPU_CTRL_TPREFIX,
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VFPU_CTRL_DPREFIX,
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@ -1204,19 +1204,19 @@ skip:
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case 0x20: // add
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case 0x21: // addu
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info.hasRelevantAddress = true;
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info.releventAddress = cpu->GetRegValue(0,MIPS_GET_RS(op))+cpu->GetRegValue(0,MIPS_GET_RT(op));
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info.relevantAddress = cpu->GetRegValue(0,MIPS_GET_RS(op))+cpu->GetRegValue(0,MIPS_GET_RT(op));
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break;
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case 0x22: // sub
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case 0x23: // subu
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info.hasRelevantAddress = true;
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info.releventAddress = cpu->GetRegValue(0,MIPS_GET_RS(op))-cpu->GetRegValue(0,MIPS_GET_RT(op));
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info.relevantAddress = cpu->GetRegValue(0,MIPS_GET_RS(op))-cpu->GetRegValue(0,MIPS_GET_RT(op));
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break;
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}
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break;
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case 0x08: // addi
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case 0x09: // adiu
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info.hasRelevantAddress = true;
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info.releventAddress = cpu->GetRegValue(0,MIPS_GET_RS(op))+((s16)(op & 0xFFFF));
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info.relevantAddress = cpu->GetRegValue(0,MIPS_GET_RS(op))+((s16)(op & 0xFFFF));
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break;
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}
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@ -1323,7 +1323,7 @@ skip:
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info.dataAddress = rs + imm16;
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info.hasRelevantAddress = true;
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info.releventAddress = info.dataAddress;
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info.relevantAddress = info.dataAddress;
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}
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return info;
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@ -154,7 +154,7 @@ namespace MIPSAnalyst
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u32 dataAddress;
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bool hasRelevantAddress;
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u32 releventAddress;
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u32 relevantAddress;
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} MipsOpcodeInfo;
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MipsOpcodeInfo GetOpcodeInfo(DebugInterface* cpu, u32 address);
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@ -74,29 +74,13 @@ int MIPS_SingleStep()
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#else
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MIPSOpcode op = Memory::Read_Opcode_JIT(mipsr4k.pc);
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#endif
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/*
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// Choke on VFPU
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MIPSInfo info = MIPSGetInfo(op);
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if (info & IS_VFPU)
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{
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if (!Core_IsStepping() && !GetAsyncKeyState(VK_LSHIFT))
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{
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Core_EnableStepping(true);
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return;
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}
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}*/
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if (mipsr4k.inDelaySlot)
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{
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if (mipsr4k.inDelaySlot) {
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MIPSInterpret(op);
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if (mipsr4k.inDelaySlot)
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{
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if (mipsr4k.inDelaySlot) {
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mipsr4k.pc = mipsr4k.nextPC;
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mipsr4k.inDelaySlot = false;
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}
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}
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else
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{
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} else {
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MIPSInterpret(op);
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}
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return 1;
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@ -872,14 +856,12 @@ namespace MIPSInt
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int pos = _POS;
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// Don't change $zr.
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if (rt == 0)
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{
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if (rt == 0) {
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PC += 4;
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return;
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}
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switch (op & 0x3f)
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{
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switch (op & 0x3f) {
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case 0x0: //ext
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{
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int size = _SIZE + 1;
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@ -1025,10 +1007,10 @@ namespace MIPSInt
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switch (op & 0x3f)
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{
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case 0: F(fd) = F(fs) + F(ft); break; //add
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case 1: F(fd) = F(fs) - F(ft); break; //sub
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case 2: F(fd) = F(fs) * F(ft); break; //mul
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case 3: F(fd) = F(fs) / F(ft); break; //div
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case 0: F(fd) = F(fs) + F(ft); break; // add.s
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case 1: F(fd) = F(fs) - F(ft); break; // sub.s
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case 2: F(fd) = F(fs) * F(ft); break; // mul.s
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case 3: F(fd) = F(fs) / F(ft); break; // div.s
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default:
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_dbg_assert_msg_(CPU,0,"Trying to interpret FPU3Op instruction that can't be interpreted");
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break;
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@ -31,8 +31,7 @@
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#include "JitCommon/JitCommon.h"
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enum MipsEncoding
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{
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enum MipsEncoding {
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Imme,
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Spec,
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Spe2,
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@ -66,8 +65,7 @@ enum MipsEncoding
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Inval = -2,
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};
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struct MIPSInstruction
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{
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struct MIPSInstruction {
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MipsEncoding altEncoding;
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const char *name;
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MIPSComp::MIPSCompileFunc compile;
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@ -152,7 +150,7 @@ const MIPSInstruction tableImmediate[64] = // xxxxxx ..... ..... ...............
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INVALID,
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INVALID,
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INSTR("swr", &Jit::Comp_ITypeMem, Dis_ITypeMem, Int_ITypeMem, IN_IMM16|IN_RS_ADDR|IN_RT|OUT_MEM|MEMTYPE_WORD),
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INSTR("cache", &Jit::Comp_Cache, Dis_Cache, Int_Cache, IN_MEM|IN_IMM16|IN_RS_ADDR|IN_OTHER|OUT_OTHER),
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INSTR("cache", &Jit::Comp_Cache, Dis_Cache, Int_Cache, IN_MEM|IN_IMM16|IN_RS_ADDR),
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//48
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INSTR("ll", &Jit::Comp_Generic, Dis_Generic, Int_StoreSync, IN_MEM|IN_IMM16|IN_RS_ADDR|OUT_RT|OUT_OTHER|MEMTYPE_WORD),
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INSTR("lwc1", &Jit::Comp_FPULS, Dis_FPULS, Int_FPULS, IN_MEM|IN_IMM16|IN_RS_ADDR|OUT_OTHER|MEMTYPE_FLOAT),
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@ -198,22 +196,22 @@ const MIPSInstruction tableSpecial[64] = // 000000 ..... ..... ..... ..... xxxxx
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INSTR("sync", &Jit::Comp_DoNothing, Dis_Generic, Int_Sync, 0),
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//16
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INSTR("mfhi", &Jit::Comp_MulDivType, Dis_FromHiloTransfer, Int_MulDivType, OUT_RD|IN_OTHER),
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INSTR("mthi", &Jit::Comp_MulDivType, Dis_ToHiloTransfer, Int_MulDivType, IN_RS|OUT_OTHER),
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INSTR("mflo", &Jit::Comp_MulDivType, Dis_FromHiloTransfer, Int_MulDivType, OUT_RD|IN_OTHER),
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INSTR("mtlo", &Jit::Comp_MulDivType, Dis_ToHiloTransfer, Int_MulDivType, IN_RS|OUT_OTHER),
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INSTR("mfhi", &Jit::Comp_MulDivType, Dis_FromHiloTransfer, Int_MulDivType, OUT_RD|IN_HI),
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INSTR("mthi", &Jit::Comp_MulDivType, Dis_ToHiloTransfer, Int_MulDivType, IN_RS|OUT_HI),
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INSTR("mflo", &Jit::Comp_MulDivType, Dis_FromHiloTransfer, Int_MulDivType, OUT_RD|IN_LO),
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INSTR("mtlo", &Jit::Comp_MulDivType, Dis_ToHiloTransfer, Int_MulDivType, IN_RS|OUT_LO),
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INVALID,
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INVALID,
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INSTR("clz", &Jit::Comp_RType2, Dis_RType2, Int_RType2, OUT_RD|IN_RS),
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INSTR("clo", &Jit::Comp_RType2, Dis_RType2, Int_RType2, OUT_RD|IN_RS),
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//24
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INSTR("mult", &Jit::Comp_MulDivType, Dis_MulDivType, Int_MulDivType, IN_RS|IN_RT|OUT_OTHER),
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INSTR("multu", &Jit::Comp_MulDivType, Dis_MulDivType, Int_MulDivType, IN_RS|IN_RT|OUT_OTHER),
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INSTR("div", &Jit::Comp_MulDivType, Dis_MulDivType, Int_MulDivType, IN_RS|IN_RT|OUT_OTHER),
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INSTR("divu", &Jit::Comp_MulDivType, Dis_MulDivType, Int_MulDivType, IN_RS|IN_RT|OUT_OTHER),
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INSTR("madd", &Jit::Comp_MulDivType, Dis_MulDivType, Int_MulDivType, IN_RS|IN_RT|IN_OTHER|OUT_OTHER),
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INSTR("maddu", &Jit::Comp_MulDivType, Dis_MulDivType, Int_MulDivType, IN_RS|IN_RT|IN_OTHER|OUT_OTHER),
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INSTR("mult", &Jit::Comp_MulDivType, Dis_MulDivType, Int_MulDivType, IN_RS|IN_RT|OUT_HI|OUT_LO),
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INSTR("multu", &Jit::Comp_MulDivType, Dis_MulDivType, Int_MulDivType, IN_RS|IN_RT|OUT_HI|OUT_LO),
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INSTR("div", &Jit::Comp_MulDivType, Dis_MulDivType, Int_MulDivType, IN_RS|IN_RT|OUT_HI|OUT_LO),
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INSTR("divu", &Jit::Comp_MulDivType, Dis_MulDivType, Int_MulDivType, IN_RS|IN_RT|OUT_HI|OUT_LO),
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INSTR("madd", &Jit::Comp_MulDivType, Dis_MulDivType, Int_MulDivType, IN_RS|IN_RT|IN_HI|IN_LO|OUT_HI|OUT_LO),
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INSTR("maddu", &Jit::Comp_MulDivType, Dis_MulDivType, Int_MulDivType, IN_RS|IN_RT|IN_HI|IN_LO|OUT_HI|OUT_LO),
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INVALID,
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INVALID,
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@ -234,8 +232,8 @@ const MIPSInstruction tableSpecial[64] = // 000000 ..... ..... ..... ..... xxxxx
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INSTR("sltu", &Jit::Comp_RType3, Dis_RType3, Int_RType3, IN_RS|IN_RT|OUT_RD),
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INSTR("max", &Jit::Comp_RType3, Dis_RType3, Int_RType3, IN_RS|IN_RT|OUT_RD),
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INSTR("min", &Jit::Comp_RType3, Dis_RType3, Int_RType3, IN_RS|IN_RT|OUT_RD),
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INSTR("msub", &Jit::Comp_MulDivType, Dis_MulDivType, Int_MulDivType, IN_RS|IN_RT|IN_OTHER|OUT_OTHER),
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INSTR("msubu", &Jit::Comp_MulDivType, Dis_MulDivType, Int_MulDivType, IN_RS|IN_RT|IN_OTHER|OUT_OTHER),
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INSTR("msub", &Jit::Comp_MulDivType, Dis_MulDivType, Int_MulDivType, IN_RS|IN_RT|IN_HI|IN_LO|OUT_HI|OUT_LO),
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INSTR("msubu", &Jit::Comp_MulDivType, Dis_MulDivType, Int_MulDivType, IN_RS|IN_RT|IN_HI|IN_LO|OUT_HI|OUT_LO),
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//48
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INSTR("tge", &Jit::Comp_Generic, Dis_RType3, 0, 0),
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@ -262,9 +260,9 @@ const MIPSInstruction tableSpecial2[64] = // 011100 ..... ..... ..... ..... xxxx
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INVALID_X_8,
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//32
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INVALID, INVALID, INVALID, INVALID,
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INSTR("mfic", &Jit::Comp_Generic, Dis_Generic, Int_Special2, 0),
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INSTR("mfic", &Jit::Comp_Generic, Dis_Generic, Int_Special2, OUT_OTHER),
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INVALID,
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INSTR("mtic", &Jit::Comp_Generic, Dis_Generic, Int_Special2, 0),
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INSTR("mtic", &Jit::Comp_Generic, Dis_Generic, Int_Special2, OUT_OTHER),
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INVALID,
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//40
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INVALID_X_8,
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@ -369,11 +367,11 @@ const MIPSInstruction tableCop2BC2[4] = // 010010 01000 ...xx ................
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const MIPSInstruction tableCop0[32] = // 010000 xxxxx ..... ................
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{
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INSTR("mfc0", &Jit::Comp_Generic, Dis_Generic, 0, OUT_RT),
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INSTR("mfc0", &Jit::Comp_Generic, Dis_Generic, 0, OUT_RT), // unused
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INVALID,
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INVALID,
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INVALID,
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INSTR("mtc0", &Jit::Comp_Generic, Dis_Generic, 0, IN_RT),
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INSTR("mtc0", &Jit::Comp_Generic, Dis_Generic, 0, IN_RT), // unused
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INVALID,
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INVALID,
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INVALID,
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@ -423,11 +421,11 @@ const MIPSInstruction tableCop0CO[64] = // 010000 1.... ..... ..... ..... xxxxxx
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const MIPSInstruction tableCop1[32] = // 010001 xxxxx ..... ..... ...........
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{
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INSTR("mfc1", &Jit::Comp_mxc1, Dis_mxc1, Int_mxc1, IN_OTHER|OUT_RT),
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INSTR("mfc1", &Jit::Comp_mxc1, Dis_mxc1, Int_mxc1, IN_FS|OUT_RT),
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INVALID,
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INSTR("cfc1", &Jit::Comp_mxc1, Dis_mxc1, Int_mxc1, IN_OTHER|IN_FPUFLAG|OUT_RT),
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INVALID,
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INSTR("mtc1", &Jit::Comp_mxc1, Dis_mxc1, Int_mxc1, IN_RT|OUT_OTHER),
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INSTR("mtc1", &Jit::Comp_mxc1, Dis_mxc1, Int_mxc1, IN_RT|OUT_FS),
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INVALID,
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INSTR("ctc1", &Jit::Comp_mxc1, Dis_mxc1, Int_mxc1, IN_RT|OUT_FPUFLAG|OUT_OTHER),
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INVALID,
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@ -455,20 +453,20 @@ const MIPSInstruction tableCop1BC[32] = // 010001 01000 xxxxx ................
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const MIPSInstruction tableCop1S[64] = // 010001 10000 ..... ..... ..... xxxxxx
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{
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INSTR("add.s", &Jit::Comp_FPU3op, Dis_FPU3op, Int_FPU3op, IN_OTHER|OUT_OTHER),
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INSTR("sub.s", &Jit::Comp_FPU3op, Dis_FPU3op, Int_FPU3op, IN_OTHER|OUT_OTHER),
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INSTR("mul.s", &Jit::Comp_FPU3op, Dis_FPU3op, Int_FPU3op, IN_OTHER|OUT_OTHER),
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INSTR("div.s", &Jit::Comp_FPU3op, Dis_FPU3op, Int_FPU3op, IN_OTHER|OUT_OTHER),
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INSTR("sqrt.s", &Jit::Comp_FPU2op, Dis_FPU2op, Int_FPU2op, IN_OTHER|OUT_OTHER),
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INSTR("abs.s", &Jit::Comp_FPU2op, Dis_FPU2op, Int_FPU2op, IN_OTHER|OUT_OTHER),
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INSTR("mov.s", &Jit::Comp_FPU2op, Dis_FPU2op, Int_FPU2op, IN_OTHER|OUT_OTHER),
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INSTR("neg.s", &Jit::Comp_FPU2op, Dis_FPU2op, Int_FPU2op, IN_OTHER|OUT_OTHER),
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INSTR("add.s", &Jit::Comp_FPU3op, Dis_FPU3op, Int_FPU3op, OUT_FD|IN_FS|IN_FT),
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INSTR("sub.s", &Jit::Comp_FPU3op, Dis_FPU3op, Int_FPU3op, OUT_FD|IN_FS|IN_FT),
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INSTR("mul.s", &Jit::Comp_FPU3op, Dis_FPU3op, Int_FPU3op, OUT_FD|IN_FS|IN_FT),
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INSTR("div.s", &Jit::Comp_FPU3op, Dis_FPU3op, Int_FPU3op, OUT_FD|IN_FS|IN_FT),
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INSTR("sqrt.s", &Jit::Comp_FPU2op, Dis_FPU2op, Int_FPU2op, OUT_FD|IN_FS),
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INSTR("abs.s", &Jit::Comp_FPU2op, Dis_FPU2op, Int_FPU2op, OUT_FD|IN_FS),
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INSTR("mov.s", &Jit::Comp_FPU2op, Dis_FPU2op, Int_FPU2op, OUT_FD|IN_FS),
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INSTR("neg.s", &Jit::Comp_FPU2op, Dis_FPU2op, Int_FPU2op, OUT_FD|IN_FS),
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//8
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INVALID, INVALID, INVALID, INVALID,
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INSTR("round.w.s", &Jit::Comp_FPU2op, Dis_FPU2op, Int_FPU2op, IN_OTHER|OUT_OTHER),
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INSTR("trunc.w.s", &Jit::Comp_FPU2op, Dis_FPU2op, Int_FPU2op, IN_OTHER|OUT_OTHER),
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INSTR("ceil.w.s", &Jit::Comp_FPU2op, Dis_FPU2op, Int_FPU2op, IN_OTHER|OUT_OTHER),
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INSTR("floor.w.s", &Jit::Comp_FPU2op, Dis_FPU2op, Int_FPU2op, IN_OTHER|OUT_OTHER),
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INSTR("round.w.s", &Jit::Comp_FPU2op, Dis_FPU2op, Int_FPU2op, OUT_FD|IN_FS),
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INSTR("trunc.w.s", &Jit::Comp_FPU2op, Dis_FPU2op, Int_FPU2op, OUT_FD|IN_FS),
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INSTR("ceil.w.s", &Jit::Comp_FPU2op, Dis_FPU2op, Int_FPU2op, OUT_FD|IN_FS),
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INSTR("floor.w.s", &Jit::Comp_FPU2op, Dis_FPU2op, Int_FPU2op, OUT_FD|IN_FS),
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//16
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INVALID_X_8,
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//24
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@ -476,29 +474,29 @@ const MIPSInstruction tableCop1S[64] = // 010001 10000 ..... ..... ..... xxxxxx
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//32
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INVALID, INVALID, INVALID, INVALID,
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//36
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INSTR("cvt.w.s", &Jit::Comp_FPU2op, Dis_FPU2op, Int_FPU2op, IN_OTHER|OUT_OTHER),
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INSTR("cvt.w.s", &Jit::Comp_FPU2op, Dis_FPU2op, Int_FPU2op, OUT_FD|IN_FS),
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INVALID,
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INSTR("dis.int", &Jit::Comp_Generic, Dis_Generic, Int_Interrupt, 0),
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INVALID,
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//40
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INVALID_X_8,
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//48 - 010001 10000 ..... ..... ..... 11xxxx
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INSTR("c.f", &Jit::Comp_FPUComp, Dis_FPUComp, Int_FPUComp, IN_OTHER|OUT_FPUFLAG),
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INSTR("c.un", &Jit::Comp_FPUComp, Dis_FPUComp, Int_FPUComp, IN_OTHER|OUT_FPUFLAG),
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INSTR("c.eq", &Jit::Comp_FPUComp, Dis_FPUComp, Int_FPUComp, IN_OTHER|OUT_FPUFLAG),
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INSTR("c.ueq", &Jit::Comp_FPUComp, Dis_FPUComp, Int_FPUComp, IN_OTHER|OUT_FPUFLAG),
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INSTR("c.olt", &Jit::Comp_FPUComp, Dis_FPUComp, Int_FPUComp, IN_OTHER|OUT_FPUFLAG),
|
||||
INSTR("c.ult", &Jit::Comp_FPUComp, Dis_FPUComp, Int_FPUComp, IN_OTHER|OUT_FPUFLAG),
|
||||
INSTR("c.ole", &Jit::Comp_FPUComp, Dis_FPUComp, Int_FPUComp, IN_OTHER|OUT_FPUFLAG),
|
||||
INSTR("c.ule", &Jit::Comp_FPUComp, Dis_FPUComp, Int_FPUComp, IN_OTHER|OUT_FPUFLAG),
|
||||
INSTR("c.sf", &Jit::Comp_FPUComp, Dis_FPUComp, Int_FPUComp, IN_OTHER|OUT_FPUFLAG),
|
||||
INSTR("c.ngle",&Jit::Comp_FPUComp, Dis_FPUComp, Int_FPUComp, IN_OTHER|OUT_FPUFLAG),
|
||||
INSTR("c.seq", &Jit::Comp_FPUComp, Dis_FPUComp, Int_FPUComp, IN_OTHER|OUT_FPUFLAG),
|
||||
INSTR("c.ngl", &Jit::Comp_FPUComp, Dis_FPUComp, Int_FPUComp, IN_OTHER|OUT_FPUFLAG),
|
||||
INSTR("c.lt", &Jit::Comp_FPUComp, Dis_FPUComp, Int_FPUComp, IN_OTHER|OUT_FPUFLAG),
|
||||
INSTR("c.nge", &Jit::Comp_FPUComp, Dis_FPUComp, Int_FPUComp, IN_OTHER|OUT_FPUFLAG),
|
||||
INSTR("c.le", &Jit::Comp_FPUComp, Dis_FPUComp, Int_FPUComp, IN_OTHER|OUT_FPUFLAG),
|
||||
INSTR("c.ngt", &Jit::Comp_FPUComp, Dis_FPUComp, Int_FPUComp, IN_OTHER|OUT_FPUFLAG),
|
||||
INSTR("c.f", &Jit::Comp_FPUComp, Dis_FPUComp, Int_FPUComp, OUT_FPUFLAG),
|
||||
INSTR("c.un", &Jit::Comp_FPUComp, Dis_FPUComp, Int_FPUComp, IN_FS|IN_FT|OUT_FPUFLAG),
|
||||
INSTR("c.eq", &Jit::Comp_FPUComp, Dis_FPUComp, Int_FPUComp, IN_FS|IN_FT|OUT_FPUFLAG),
|
||||
INSTR("c.ueq", &Jit::Comp_FPUComp, Dis_FPUComp, Int_FPUComp, IN_FS|IN_FT|OUT_FPUFLAG),
|
||||
INSTR("c.olt", &Jit::Comp_FPUComp, Dis_FPUComp, Int_FPUComp, IN_FS|IN_FT|OUT_FPUFLAG),
|
||||
INSTR("c.ult", &Jit::Comp_FPUComp, Dis_FPUComp, Int_FPUComp, IN_FS|IN_FT|OUT_FPUFLAG),
|
||||
INSTR("c.ole", &Jit::Comp_FPUComp, Dis_FPUComp, Int_FPUComp, IN_FS|IN_FT|OUT_FPUFLAG),
|
||||
INSTR("c.ule", &Jit::Comp_FPUComp, Dis_FPUComp, Int_FPUComp, IN_FS|IN_FT|OUT_FPUFLAG),
|
||||
INSTR("c.sf", &Jit::Comp_FPUComp, Dis_FPUComp, Int_FPUComp, OUT_FPUFLAG),
|
||||
INSTR("c.ngle",&Jit::Comp_FPUComp, Dis_FPUComp, Int_FPUComp, IN_FS|IN_FT|OUT_FPUFLAG),
|
||||
INSTR("c.seq", &Jit::Comp_FPUComp, Dis_FPUComp, Int_FPUComp, IN_FS|IN_FT|OUT_FPUFLAG),
|
||||
INSTR("c.ngl", &Jit::Comp_FPUComp, Dis_FPUComp, Int_FPUComp, IN_FS|IN_FT|OUT_FPUFLAG),
|
||||
INSTR("c.lt", &Jit::Comp_FPUComp, Dis_FPUComp, Int_FPUComp, IN_FS|IN_FT|OUT_FPUFLAG),
|
||||
INSTR("c.nge", &Jit::Comp_FPUComp, Dis_FPUComp, Int_FPUComp, IN_FS|IN_FT|OUT_FPUFLAG),
|
||||
INSTR("c.le", &Jit::Comp_FPUComp, Dis_FPUComp, Int_FPUComp, IN_FS|IN_FT|OUT_FPUFLAG),
|
||||
INSTR("c.ngt", &Jit::Comp_FPUComp, Dis_FPUComp, Int_FPUComp, IN_FS|IN_FT|OUT_FPUFLAG),
|
||||
};
|
||||
|
||||
const MIPSInstruction tableCop1W[64] = // 010001 10100 ..... ..... ..... xxxxxx
|
||||
@ -511,7 +509,7 @@ const MIPSInstruction tableCop1W[64] = // 010001 10100 ..... ..... ..... xxxxxx
|
||||
//24
|
||||
INVALID_X_8,
|
||||
//32
|
||||
INSTR("cvt.s.w", &Jit::Comp_FPU2op, Dis_FPU2op, Int_FPU2op, IN_OTHER|OUT_OTHER),
|
||||
INSTR("cvt.s.w", &Jit::Comp_FPU2op, Dis_FPU2op, Int_FPU2op, OUT_FD|IN_FS),
|
||||
INVALID, INVALID, INVALID,
|
||||
//36
|
||||
INVALID,
|
||||
@ -890,8 +888,6 @@ const MIPSInstruction *mipsTables[NumEncodings] =
|
||||
0,
|
||||
};
|
||||
|
||||
|
||||
|
||||
//arm encoding table
|
||||
//const MIPSInstruction mipsinstructions[] =
|
||||
//{
|
||||
|
||||
@ -25,14 +25,14 @@ struct MIPSInfo {
|
||||
value = 0;
|
||||
}
|
||||
|
||||
explicit MIPSInfo(u32 v) : value(v) {
|
||||
explicit MIPSInfo(u64 v) : value(v) {
|
||||
}
|
||||
|
||||
u32 operator & (const u32 &arg) const {
|
||||
u64 operator & (const u32 &arg) const {
|
||||
return value & arg;
|
||||
}
|
||||
|
||||
u32 value;
|
||||
u64 value;
|
||||
};
|
||||
|
||||
#define CONDTYPE_MASK 0x00000007
|
||||
@ -49,44 +49,59 @@ struct MIPSInfo {
|
||||
// as long as the other flags are checked,
|
||||
// there is no way to misinterpret these
|
||||
// as CONDTYPE_X
|
||||
#define MEMTYPE_MASK 0x00000007
|
||||
#define MEMTYPE_BYTE 0x00000001
|
||||
#define MEMTYPE_HWORD 0x00000002
|
||||
#define MEMTYPE_WORD 0x00000003
|
||||
#define MEMTYPE_FLOAT 0x00000004
|
||||
#define MEMTYPE_VQUAD 0x00000005
|
||||
#define MEMTYPE_MASK 0x00000007ULL
|
||||
#define MEMTYPE_BYTE 0x00000001ULL
|
||||
#define MEMTYPE_HWORD 0x00000002ULL
|
||||
#define MEMTYPE_WORD 0x00000003ULL
|
||||
#define MEMTYPE_FLOAT 0x00000004ULL
|
||||
#define MEMTYPE_VQUAD 0x00000005ULL
|
||||
|
||||
#define IS_CONDMOVE 0x00000008
|
||||
#define DELAYSLOT 0x00000010
|
||||
#define BAD_INSTRUCTION 0x00000020
|
||||
#define LIKELY 0x00000040
|
||||
#define IS_CONDBRANCH 0x00000080
|
||||
#define IS_JUMP 0x00000100
|
||||
#define IS_CONDMOVE 0x00000008ULL
|
||||
#define DELAYSLOT 0x00000010ULL
|
||||
#define BAD_INSTRUCTION 0x00000020ULL
|
||||
#define LIKELY 0x00000040ULL
|
||||
#define IS_CONDBRANCH 0x00000080ULL
|
||||
#define IS_JUMP 0x00000100ULL
|
||||
|
||||
#define IN_RS 0x00000200
|
||||
#define IN_RS_ADDR (0x00000400 | IN_RS)
|
||||
#define IN_RS_SHIFT (0x00000800 | IN_RS)
|
||||
#define IN_RT 0x00001000
|
||||
#define IN_SA 0x00002000
|
||||
#define IN_IMM16 0x00004000
|
||||
#define IN_IMM26 0x00008000
|
||||
#define IN_MEM 0x00010000
|
||||
#define IN_OTHER 0x00020000
|
||||
#define IN_FPUFLAG 0x00040000
|
||||
#define IN_VFPU_CC 0x00080000
|
||||
#define IN_RS 0x00000200ULL
|
||||
#define IN_RS_ADDR (0x00000400ULL | IN_RS)
|
||||
#define IN_RS_SHIFT (0x00000800ULL | IN_RS)
|
||||
#define IN_RT 0x00001000ULL
|
||||
#define IN_SA 0x00002000ULL
|
||||
#define IN_IMM16 0x00004000ULL
|
||||
#define IN_IMM26 0x00008000ULL
|
||||
#define IN_MEM 0x00010000ULL
|
||||
#define IN_OTHER 0x00020000ULL
|
||||
#define IN_FPUFLAG 0x00040000ULL
|
||||
#define IN_VFPU_CC 0x00080000ULL
|
||||
|
||||
#define OUT_RT 0x00100000
|
||||
#define OUT_RD 0x00200000
|
||||
#define OUT_RA 0x00400000
|
||||
#define OUT_MEM 0x00800000
|
||||
#define OUT_OTHER 0x01000000
|
||||
#define OUT_FPUFLAG 0x02000000
|
||||
#define OUT_VFPU_CC 0x04000000
|
||||
#define OUT_EAT_PREFIX 0x08000000
|
||||
#define OUT_RT 0x00100000ULL
|
||||
#define OUT_RD 0x00200000ULL
|
||||
#define OUT_RA 0x00400000ULL
|
||||
#define OUT_MEM 0x00800000ULL
|
||||
#define OUT_OTHER 0x01000000ULL
|
||||
#define OUT_FPUFLAG 0x02000000ULL
|
||||
#define OUT_VFPU_CC 0x04000000ULL
|
||||
#define OUT_EAT_PREFIX 0x08000000ULL
|
||||
|
||||
#define VFPU_NO_PREFIX 0x10000000
|
||||
#define IS_VFPU 0x20000000
|
||||
#define IS_FPU 0x40000000
|
||||
#define VFPU_NO_PREFIX 0x10000000ULL
|
||||
#define IS_VFPU 0x20000000ULL
|
||||
#define IS_FPU 0x40000000ULL
|
||||
|
||||
#define IN_FS 0x000100000000ULL
|
||||
#define IN_FT 0x000200000000ULL
|
||||
#define IN_LO 0x000400000000ULL
|
||||
#define IN_HI 0x000800000000ULL
|
||||
|
||||
#define OUT_FD 0x001000000000ULL
|
||||
#define OUT_FS 0x002000000000ULL
|
||||
#define OUT_LO 0x004000000000ULL
|
||||
#define OUT_HI 0x008000000000ULL
|
||||
|
||||
#define IN_VS 0x010000000000ULL
|
||||
#define IN_VT 0x020000000000ULL
|
||||
|
||||
#define OUT_VD 0x100000000000ULL
|
||||
|
||||
#ifndef CDECL
|
||||
#define CDECL
|
||||
|
||||
@ -643,7 +643,7 @@ void CtrlDisAsmView::followBranch()
|
||||
} else if (line.info.hasRelevantAddress)
|
||||
{
|
||||
// well, not exactly a branch, but we can do something anyway
|
||||
SendMessage(GetParent(wnd),WM_DEB_GOTOHEXEDIT,line.info.releventAddress,0);
|
||||
SendMessage(GetParent(wnd),WM_DEB_GOTOHEXEDIT,line.info.relevantAddress,0);
|
||||
SetFocus(wnd);
|
||||
}
|
||||
} else if (line.type == DISTYPE_DATA)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user