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Build: More consistently avoid _M_ defines.

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We use PPSSPP_ARCH in several places already, this makes it more complete.
This commit is contained in:
Unknown W. Brackets 2021-03-02 21:49:21 -08:00
parent d9aecffd72
commit 4178f09e57
28 changed files with 102 additions and 90 deletions
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15
Common/ABI.cpp
View File

@ -15,7 +15,8 @@
// Official SVN repository and contact information can be found at
// http://code.google.com/p/dolphin-emu/
#if defined(_M_IX86) || defined(_M_X64)
#include "ppsspp_config.h"
#if PPSSPP_ARCH(X86) || PPSSPP_ARCH(AMD64)
#include "x64Emitter.h"
#include "ABI.h"
@ -27,9 +28,9 @@ using namespace Gen;
// Sets up a __cdecl function.
void XEmitter::ABI_EmitPrologue(int maxCallParams)
{
#ifdef _M_IX86
#if PPSSPP_ARCH(X86)
// Don't really need to do anything
#elif defined(_M_X64)
#elif PPSSPP_ARCH(AMD64)
#if _WIN32
int stacksize = ((maxCallParams + 1) & ~1) * 8 + 8;
// Set up a stack frame so that we can call functions
@ -43,9 +44,9 @@ void XEmitter::ABI_EmitPrologue(int maxCallParams)
void XEmitter::ABI_EmitEpilogue(int maxCallParams)
{
#ifdef _M_IX86
#if PPSSPP_ARCH(X86)
RET();
#elif defined(_M_X64)
#elif PPSSPP_ARCH(AMD64)
#ifdef _WIN32
int stacksize = ((maxCallParams+1)&~1)*8 + 8;
ADD(64, R(RSP), Imm8(stacksize));
@ -58,7 +59,7 @@ void XEmitter::ABI_EmitEpilogue(int maxCallParams)
#endif
}
#ifdef _M_IX86 // All32
#if PPSSPP_ARCH(X86) // All32
// Shared code between Win32 and Unix32
void XEmitter::ABI_CallFunction(const void *func) {
@ -681,4 +682,4 @@ void XEmitter::ABI_RestoreStack(unsigned int /*frameSize*/) {
#endif // 32bit
#endif // defined(_M_IX86) || defined(_M_X64)
#endif // PPSSPP_ARCH(X86) || PPSSPP_ARCH(AMD64)

5
Common/ABI.h
View File

@ -17,6 +17,7 @@
#pragma once
#include "ppsspp_config.h"
#include "Common.h"
// x86/x64 ABI:s, and helpers to help follow them when JIT-ing code.
@ -44,7 +45,7 @@
// Callee-save: RBX RBP R12 R13 R14 R15
// Parameters: RDI RSI RDX RCX R8 R9
#ifdef _M_IX86 // 32 bit calling convention, shared by all
#if PPSSPP_ARCH(X86) // 32 bit calling convention, shared by all
// 32-bit don't pass parameters in regs, but these are convenient to have anyway when we have to
// choose regs to put stuff in.
@ -55,7 +56,7 @@
// 32-bit bog standard cdecl, shared between linux and windows
// MacOSX 32-bit is same as System V with a few exceptions that we probably don't care much about.
#elif _M_X64 // 64 bit calling convention
#elif PPSSPP_ARCH(AMD64) // 64 bit calling convention
#ifdef _WIN32 // 64-bit Windows - the really exotic calling convention

3
Common/BitSet.h
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@ -2,6 +2,7 @@
#pragma once
#include "ppsspp_config.h"
#include <cstdint>
#include <cstdlib> // for byte swapping
#include <cstddef>
@ -27,7 +28,7 @@ inline int LeastSignificantSetBit(u32 val)
_BitScanForward(&index, val);
return (int)index;
}
#ifdef _M_X64
#if PPSSPP_ARCH(AMD64)
inline int LeastSignificantSetBit(u64 val)
{
unsigned long index;

12
Common/CPUDetect.cpp
View File

@ -16,9 +16,9 @@
// http://code.google.com/p/dolphin-emu/
// Reference : https://stackoverflow.com/questions/6121792/how-to-check-if-a-cpu-supports-the-sse3-instruction-set
#if defined(_M_IX86) || defined(_M_X64)
#include "ppsspp_config.h"
#if PPSSPP_ARCH(X86) || PPSSPP_ARCH(AMD64)
#ifdef __ANDROID__
#include <sys/stat.h>
#include <fcntl.h>
@ -141,9 +141,9 @@ static std::vector<int> ParseCPUList(const std::string &filename) {
// Detects the various cpu features
void CPUInfo::Detect() {
memset(this, 0, sizeof(*this));
#ifdef _M_IX86
#if PPSSPP_ARCH(X86)
Mode64bit = false;
#elif defined (_M_X64)
#elif PPSSPP_ARCH(AMD64)
Mode64bit = true;
OS64bit = true;
#endif
@ -151,7 +151,7 @@ void CPUInfo::Detect() {
#if PPSSPP_PLATFORM(UWP)
OS64bit = Mode64bit; // TODO: Not always accurate!
#elif defined(_WIN32) && defined(_M_IX86)
#elif defined(_WIN32) && PPSSPP_ARCH(X86)
BOOL f64 = false;
IsWow64Process(GetCurrentProcess(), &f64);
OS64bit = (f64 == TRUE) ? true : false;
@ -441,4 +441,4 @@ std::string CPUInfo::Summarize()
return sum;
}
#endif // defined(_M_IX86) || defined(_M_X64)
#endif // PPSSPP_ARCH(X86) || PPSSPP_ARCH(AMD64)

8
Common/MemoryUtil.cpp
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@ -87,7 +87,7 @@ static uint32_t ConvertProtFlagsUnix(uint32_t flags) {
#endif
#if defined(_WIN32) && defined(_M_X64)
#if defined(_WIN32) && PPSSPP_ARCH(AMD64)
static uintptr_t last_executable_addr;
static void *SearchForFreeMem(size_t size) {
if (!last_executable_addr)
@ -128,7 +128,7 @@ void *AllocateExecutableMemory(size_t size) {
prot = PAGE_READWRITE;
if (sys_info.dwPageSize == 0)
GetSystemInfo(&sys_info);
#if defined(_M_X64)
#if PPSSPP_ARCH(AMD64)
if ((uintptr_t)&hint_location > 0xFFFFFFFFULL) {
size_t aligned_size = ppsspp_round_page(size);
#if 1 // Turn off to hunt for RIP bugs on x86-64.
@ -159,7 +159,7 @@ void *AllocateExecutableMemory(size_t size) {
}
#else
static char *map_hint = 0;
#if defined(_M_X64)
#if PPSSPP_ARCH(AMD64)
// Try to request one that is close to our memory location if we're in high memory.
// We use a dummy global variable to give us a good location to start from.
if (!map_hint) {
@ -190,7 +190,7 @@ void *AllocateExecutableMemory(size_t size) {
ERROR_LOG(MEMMAP, "Failed to allocate executable memory (%d) errno=%d", (int)size, errno);
}
#if defined(_M_X64) && !defined(_WIN32)
#if PPSSPP_ARCH(AMD64) && !defined(_WIN32)
else if ((uintptr_t)map_hint <= 0xFFFFFFFF) {
// Round up if we're below 32-bit mark, probably allocating sequentially.
map_hint += ppsspp_round_page(size);

19
Common/Thunk.cpp
View File

@ -15,6 +15,7 @@
// Official SVN repository and contact information can be found at
// http://code.google.com/p/dolphin-emu/
#include "ppsspp_config.h"
#include "MemoryUtil.h"
#include "ABI.h"
#include "Thunk.h"
@ -23,7 +24,7 @@
namespace {
#ifndef _M_X64
#if !PPSSPP_ARCH(AMD64)
alignas(32) static u8 saved_fp_state[16 * 4 * 4];
alignas(32) static u8 saved_gpr_state[16 * 8];
static u16 saved_mxcsr;
@ -35,7 +36,7 @@ using namespace Gen;
void ThunkManager::Init()
{
#ifdef _M_X64
#if PPSSPP_ARCH(AMD64)
// Account for the return address and "home space" on Windows (which needs to be at the bottom.)
const int stackOffset = ThunkStackOffset();
int stackPosition;
@ -44,7 +45,7 @@ void ThunkManager::Init()
AllocCodeSpace(THUNK_ARENA_SIZE);
BeginWrite();
save_regs = GetCodePtr();
#ifdef _M_X64
#if PPSSPP_ARCH(AMD64)
for (int i = 2; i < ABI_GetNumXMMRegs(); i++)
MOVAPS(MDisp(RSP, stackOffset + (i - 2) * 16), (X64Reg)(XMM0 + i));
stackPosition = (ABI_GetNumXMMRegs() - 2) * 2;
@ -70,7 +71,7 @@ void ThunkManager::Init()
RET();
load_regs = GetCodePtr();
#ifdef _M_X64
#if PPSSPP_ARCH(AMD64)
for (int i = 2; i < ABI_GetNumXMMRegs(); i++)
MOVAPS((X64Reg)(XMM0 + i), MDisp(RSP, stackOffset + (i - 2) * 16));
stackPosition = (ABI_GetNumXMMRegs() - 2) * 2;
@ -112,7 +113,7 @@ void ThunkManager::Shutdown()
int ThunkManager::ThunkBytesNeeded()
{
int space = (ABI_GetNumXMMRegs() - 2) * 16;
#ifdef _M_X64
#if PPSSPP_ARCH(AMD64)
// MXCSR
space += 8;
space += 7 * 8;
@ -131,7 +132,7 @@ int ThunkManager::ThunkBytesNeeded()
int ThunkManager::ThunkStackOffset()
{
#ifdef _M_X64
#if PPSSPP_ARCH(AMD64)
#ifdef _WIN32
return 0x28;
#else
@ -154,7 +155,7 @@ const void *ThunkManager::ProtectFunction(const void *function, int num_params)
const u8 *call_point = GetCodePtr();
Enter(this, true);
#ifdef _M_X64
#if PPSSPP_ARCH(AMD64)
ABI_CallFunction(function);
#else
// Since parameters are in the previous stack frame, not in registers, this takes some
@ -180,7 +181,7 @@ const void *ThunkManager::ProtectFunction(const void *function, int num_params)
void ThunkManager::Enter(ThunkEmitter *emit, bool withinCall)
{
#ifdef _M_X64
#if PPSSPP_ARCH(AMD64)
// Make sure to align stack.
emit->SUB(64, R(ESP), Imm32(ThunkStackOffset() + ThunkBytesNeeded() + (withinCall ? 0 : 8)));
emit->ABI_CallFunction(save_regs);
@ -191,7 +192,7 @@ void ThunkManager::Enter(ThunkEmitter *emit, bool withinCall)
void ThunkManager::Leave(ThunkEmitter *emit, bool withinCall)
{
#ifdef _M_X64
#if PPSSPP_ARCH(AMD64)
emit->ABI_CallFunction(load_regs);
emit->ADD(64, R(ESP), Imm32(ThunkStackOffset() + ThunkBytesNeeded() + (withinCall ? 0 : 8)));
#else

7
Common/x64Emitter.cpp
View File

@ -15,6 +15,7 @@
// Official SVN repository and contact information can be found at
// http://code.google.com/p/dolphin-emu/
#include "ppsspp_config.h"
#include <cstring>
#include "x64Emitter.h"
@ -160,7 +161,7 @@ void XEmitter::WriteSIB(int scale, int index, int base)
void OpArg::WriteRex(XEmitter *emit, int opBits, int bits, int customOp) const
{
if (customOp == -1) customOp = operandReg;
#ifdef _M_X64
#if PPSSPP_ARCH(AMD64)
u8 op = 0x40;
// REX.W (whether operation is a 64-bit operation)
if (opBits == 64) op |= 8;
@ -232,7 +233,7 @@ void OpArg::WriteRest(XEmitter *emit, int extraBytes, X64Reg _operandReg,
_offsetOrBaseReg = 5;
emit->WriteModRM(0, _operandReg, _offsetOrBaseReg);
//TODO : add some checks
#ifdef _M_X64
#if PPSSPP_ARCH(AMD64)
u64 ripAddr = (u64)emit->GetCodePointer() + 4 + extraBytes;
s64 distance = (s64)offset - (s64)ripAddr;
_assert_msg_(
@ -1451,7 +1452,7 @@ void XEmitter::MOVD_xmm(const OpArg &arg, X64Reg src) {WriteSSEOp(0x66, 0x7E, sr
void XEmitter::MOVQ_xmm(X64Reg dest, OpArg arg)
{
#ifdef _M_X64
#if PPSSPP_ARCH(AMD64)
// Alternate encoding
// This does not display correctly in MSVC's debugger, it thinks it's a MOVD
arg.operandReg = dest;

4
Common/x64Emitter.h
View File

@ -1057,7 +1057,7 @@ public:
void ABI_EmitPrologue(int maxCallParams);
void ABI_EmitEpilogue(int maxCallParams);
#ifdef _M_IX86
#if PPSSPP_ARCH(X86)
inline int ABI_GetNumXMMRegs() { return 8; }
#else
inline int ABI_GetNumXMMRegs() { return 16; }
@ -1075,7 +1075,7 @@ public:
bool RipAccessible(const void *ptr) const {
// For debugging
// return false;
#ifdef _M_IX86
#if PPSSPP_ARCH(X86)
return true;
#else
ptrdiff_t diff = GetCodePtr() - (const uint8_t *)ptr;

2
Core/Config.cpp
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@ -988,7 +988,7 @@ static ConfigSetting networkSettings[] = {
static int DefaultPSPModel() {
// TODO: Can probably default this on, but not sure about its memory differences.
#if !defined(_M_X64) && !defined(_WIN32)
#if !PPSSPP_ARCH(AMD64) && !defined(_WIN32)
return PSP_MODEL_FAT;
#else
return PSP_MODEL_SLIM;

3
Core/Debugger/DisassemblyManager.cpp
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@ -15,6 +15,7 @@
// Official git repository and contact information can be found at
// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
#include "ppsspp_config.h"
#include <string>
#include <algorithm>
#include <map>
@ -43,7 +44,7 @@ bool isInInterval(u32 start, u32 size, u32 value)
static HashType computeHash(u32 address, u32 size)
{
#ifdef _M_X64
#if PPSSPP_ARCH(AMD64)
return XXH3_64bits(Memory::GetPointer(address), size);
#else
return XXH3_64bits(Memory::GetPointer(address), size) & 0xFFFFFFFF;

3
Core/Debugger/DisassemblyManager.h
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@ -17,12 +17,13 @@
#pragma once
#include "ppsspp_config.h"
#include <mutex>
#include "Common/CommonTypes.h"
#include "Core/Debugger/SymbolMap.h"
#include "Core/MIPS/MIPSAnalyst.h"
#ifdef _M_X64
#if PPSSPP_ARCH(AMD64)
typedef u64 HashType;
#else
typedef u32 HashType;

9
Core/HLE/ReplaceTables.cpp
View File

@ -15,6 +15,7 @@
// Official git repository and contact information can be found at
// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
#include "ppsspp_config.h"
#include <algorithm>
#include <map>
#include <unordered_map>
@ -39,7 +40,7 @@
#include "GPU/GPUInterface.h"
#include "GPU/GPUState.h"
#if defined(_M_IX86) || defined(_M_X64)
#if PPSSPP_ARCH(X86) || PPSSPP_ARCH(AMD64)
#include <emmintrin.h>
#endif
@ -451,7 +452,7 @@ static int Replace_gta_dl_write_matrix() {
return 38;
}
#if defined(_M_IX86) || defined(_M_X64)
#if PPSSPP_ARCH(X86) || PPSSPP_ARCH(AMD64)
__m128i topBytes = _mm_set1_epi32(matrix);
__m128i m0 = _mm_loadu_si128((const __m128i *)src);
__m128i m1 = _mm_loadu_si128((const __m128i *)(src + 4));
@ -533,7 +534,7 @@ static int Replace_dl_write_matrix() {
if (count == 16) {
// Ultra SIMD friendly! These intrinsics generate pretty much perfect code,
// no point in hand rolling.
#if defined(_M_IX86) || defined(_M_X64)
#if PPSSPP_ARCH(X86) || PPSSPP_ARCH(AMD64)
__m128i topBytes = _mm_set1_epi32(matrix);
__m128i m0 = _mm_loadu_si128((const __m128i *)src);
__m128i m1 = _mm_loadu_si128((const __m128i *)(src + 4));
@ -569,7 +570,7 @@ static int Replace_dl_write_matrix() {
}
#endif
} else {
#if defined(_M_IX86) || defined(_M_X64)
#if PPSSPP_ARCH(X86) || PPSSPP_ARCH(AMD64)
__m128i topBytes = _mm_set1_epi32(matrix);
__m128i m0 = _mm_loadu_si128((const __m128i *)src);
__m128i m1 = _mm_loadu_si128((const __m128i *)(src + 4));

10
Core/MIPS/x86/Asm.cpp
View File

@ -111,7 +111,7 @@ void Jit::GenerateFixedCode(JitOptions &jo) {
enterDispatcher = AlignCode16();
ABI_PushAllCalleeSavedRegsAndAdjustStack();
#ifdef _M_X64
#if PPSSPP_ARCH(AMD64)
// Two statically allocated registers.
MOV(64, R(MEMBASEREG), ImmPtr(Memory::base));
uintptr_t jitbase = (uintptr_t)GetBasePtr();
@ -162,10 +162,10 @@ void Jit::GenerateFixedCode(JitOptions &jo) {
AND(32, R(EAX), Imm32(Memory::MEMVIEW32_MASK));
#endif
dispatcherFetch = GetCodePtr();
#ifdef _M_IX86
#if PPSSPP_ARCH(X86)
_assert_msg_( Memory::base != 0, "Memory base bogus");
MOV(32, R(EAX), MDisp(EAX, (u32)Memory::base));
#elif _M_X64
#elif PPSSPP_ARCH(AMD64)
MOV(32, R(EAX), MComplex(MEMBASEREG, RAX, SCALE_1, 0));
#endif
MOV(32, R(EDX), R(EAX));
@ -178,9 +178,9 @@ void Jit::GenerateFixedCode(JitOptions &jo) {
}
//grab from list and jump to it
AND(32, R(EAX), Imm32(MIPS_EMUHACK_VALUE_MASK));
#ifdef _M_IX86
#if PPSSPP_ARCH(X86)
ADD(32, R(EAX), ImmPtr(GetBasePtr()));
#elif _M_X64
#elif PPSSPP_ARCH(AMD64)
if (jo.reserveR15ForAsm)
ADD(64, R(RAX), R(JITBASEREG));
else

2
Core/MIPS/x86/CompALU.cpp
View File

@ -53,7 +53,7 @@ namespace MIPSComp
using namespace X64JitConstants;
static bool HasLowSubregister(OpArg arg) {
#ifndef _M_X64
#if !PPSSPP_ARCH(AMD64)
// Can't use ESI or EDI (which we use), no 8-bit versions. Only these.
if (!arg.IsSimpleReg(EAX) && !arg.IsSimpleReg(EBX) && !arg.IsSimpleReg(ECX) && !arg.IsSimpleReg(EDX)) {
return false;

4
Core/MIPS/x86/CompLoadStore.cpp
View File

@ -94,7 +94,7 @@ namespace MIPSComp {
gpr.MapReg(rt, true, false);
}
#ifdef _M_IX86
#if PPSSPP_ARCH(X86)
// We use EDX so we can have DL for 8-bit ops.
const bool needSwap = bits == 8 && !gpr.R(rt).IsSimpleReg(EDX) && !gpr.R(rt).IsSimpleReg(ECX);
if (needSwap)
@ -144,7 +144,7 @@ namespace MIPSComp {
X64Reg shiftReg = ECX;
gpr.FlushLockX(ECX, EDX);
#ifdef _M_X64
#if PPSSPP_ARCH(AMD64)
// On x64, we need ECX for CL, but it's also the first arg and gets lost. Annoying.
gpr.FlushLockX(R9);
shiftReg = R9;

12
Core/MIPS/x86/CompVFPU.cpp
View File

@ -324,7 +324,7 @@ void Jit::Comp_SVQ(MIPSOpcode op) {
FixupBranch next = J_CC(CC_NE);
auto PSPMemAddr = [](X64Reg scaled, int offset) {
#ifdef _M_IX86
#if PPSSPP_ARCH(X86)
return MDisp(scaled, (u32)Memory::base + offset);
#else
return MComplex(MEMBASEREG, scaled, 1, offset);
@ -2164,7 +2164,7 @@ union u32float {
}
};
#ifdef _M_X64
#if PPSSPP_ARCH(AMD64)
typedef float SinCosArg;
#else
typedef u32float SinCosArg;
@ -2202,7 +2202,7 @@ void Jit::Comp_VV2Op(MIPSOpcode op) {
DISABLE;
auto trigCallHelper = [this](void (*sinCosFunc)(SinCosArg, float *output), u8 sreg) {
#ifdef _M_X64
#if PPSSPP_ARCH(AMD64)
MOVSS(XMM0, fpr.V(sreg));
// TODO: This reg might be different on Linux...
#ifdef _WIN32
@ -2910,7 +2910,7 @@ void Jit::Comp_Vmmul(MIPSOpcode op) {
// Map the D column.
u8 dcol[4];
GetVectorRegs(dcol, vsz, dcols[i]);
#ifndef _M_X64
#if !PPSSPP_ARCH(AMD64)
fpr.MapRegsVS(dcol, vsz, MAP_DIRTY | MAP_NOINIT | MAP_NOLOCK);
#else
fpr.MapRegsVS(dcol, vsz, MAP_DIRTY | MAP_NOINIT);
@ -2923,7 +2923,7 @@ void Jit::Comp_Vmmul(MIPSOpcode op) {
}
}
#ifndef _M_X64
#if !PPSSPP_ARCH(AMD64)
fpr.ReleaseSpillLocks();
#endif
if (transposeDest) {
@ -3566,7 +3566,7 @@ void Jit::Comp_VRot(MIPSOpcode op) {
bool negSin1 = (imm & 0x10) ? true : false;
#ifdef _M_X64
#if PPSSPP_ARCH(AMD64)
#ifdef _WIN32
LEA(64, RDX, MIPSSTATE_VAR(sincostemp));
#else

4
Core/MIPS/x86/Jit.cpp
View File

@ -216,7 +216,7 @@ void Jit::ClearCache()
void Jit::SaveFlags() {
PUSHF();
#if defined(_M_X64)
#if PPSSPP_ARCH(AMD64)
// On X64, the above misaligns the stack. However there might be a cheaper solution than this.
POP(64, R(EAX));
MOV(64, MIPSSTATE_VAR(saved_flags), R(EAX));
@ -224,7 +224,7 @@ void Jit::SaveFlags() {
}
void Jit::LoadFlags() {
#if defined(_M_X64)
#if PPSSPP_ARCH(AMD64)
MOV(64, R(EAX), MIPSSTATE_VAR(saved_flags));
PUSH(64, R(EAX));
#endif

10
Core/MIPS/x86/RegCache.cpp
View File

@ -34,18 +34,18 @@ using namespace X64JitConstants;
static const X64Reg allocationOrder[] = {
// R12, when used as base register, for example in a LEA, can generate bad code! Need to look into this.
// On x64, RCX and RDX are the first args. CallProtectedFunction() assumes they're not regcached.
#ifdef _M_X64
#if PPSSPP_ARCH(AMD64)
#ifdef _WIN32
RSI, RDI, R8, R9, R10, R11, R12, R13,
#else
RBP, R8, R9, R10, R11, R12, R13,
#endif
#elif _M_IX86
#elif PPSSPP_ARCH(X86)
ESI, EDI, EDX, ECX, EBX,
#endif
};
#ifdef _M_X64
#if PPSSPP_ARCH(AMD64)
static X64Reg allocationOrderR15[ARRAY_SIZE(allocationOrder) + 1] = {INVALID_REG};
#endif
@ -58,7 +58,7 @@ GPRRegCache::GPRRegCache() {
}
void GPRRegCache::Start(MIPSState *mipsState, MIPSComp::JitState *js, MIPSComp::JitOptions *jo, MIPSAnalyst::AnalysisResults &stats) {
#ifdef _M_X64
#if PPSSPP_ARCH(AMD64)
if (allocationOrderR15[0] == INVALID_REG) {
memcpy(allocationOrderR15, allocationOrder, sizeof(allocationOrder));
allocationOrderR15[ARRAY_SIZE(allocationOrderR15) - 1] = R15;
@ -305,7 +305,7 @@ u32 GPRRegCache::GetImm(MIPSGPReg preg) const {
}
const X64Reg *GPRRegCache::GetAllocationOrder(int &count) {
#ifdef _M_X64
#if PPSSPP_ARCH(AMD64)
if (!jo_->reserveR15ForAsm) {
count = ARRAY_SIZE(allocationOrderR15);
return allocationOrderR15;

7
Core/MIPS/x86/RegCache.h
View File

@ -17,12 +17,13 @@
#pragma once
#include "ppsspp_config.h"
#include "Common/x64Emitter.h"
#include "Core/MIPS/MIPS.h"
#include "Core/MIPS/MIPSAnalyst.h"
namespace X64JitConstants {
#ifdef _M_X64
#if PPSSPP_ARCH(AMD64)
const Gen::X64Reg MEMBASEREG = Gen::RBX;
const Gen::X64Reg CTXREG = Gen::R14;
const Gen::X64Reg JITBASEREG = Gen::R15;
@ -34,9 +35,9 @@ namespace X64JitConstants {
const Gen::X64Reg TEMPREG = Gen::EAX;
const int NUM_MIPS_GPRS = 36;
#ifdef _M_X64
#if PPSSPP_ARCH(AMD64)
const u32 NUM_X_REGS = 16;
#elif _M_IX86
#elif PPSSPP_ARCH(X86)
const u32 NUM_X_REGS = 8;
#endif
}

4
Core/MIPS/x86/RegCacheFPU.cpp
View File

@ -1020,9 +1020,9 @@ int FPURegCache::SanityCheck() const {
const int *FPURegCache::GetAllocationOrder(int &count) {
static const int allocationOrder[] = {
#ifdef _M_X64
#if PPSSPP_ARCH(AMD64)
XMM6, XMM7, XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, XMM2, XMM3, XMM4, XMM5
#elif _M_IX86
#elif PPSSPP_ARCH(X86)
XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
#endif
};

6
Core/MIPS/x86/RegCacheFPU.h
View File

@ -43,14 +43,16 @@
// take into account in which XMM registers the values are. Fallback: Just dump out the values
// and do it the old way.
#include "ppsspp_config.h"
enum {
TEMP0 = 32 + 128,
NUM_MIPS_FPRS = 32 + 128 + NUM_X86_FPU_TEMPS,
};
#ifdef _M_X64
#if PPSSPP_ARCH(AMD64)
#define NUM_X_FPREGS 16
#elif _M_IX86
#elif PPSSPP_ARCH(X86)
#define NUM_X_FPREGS 8
#endif

6
Core/System.cpp
View File

@ -230,7 +230,7 @@ bool CPU_Init() {
std::string filename = coreParameter.fileToStart;
loadedFile = ResolveFileLoaderTarget(ConstructFileLoader(filename));
#ifdef _M_X64
#if PPSSPP_ARCH(AMD64)
if (g_Config.bCacheFullIsoInRam) {
loadedFile = new RamCachingFileLoader(loadedFile);
}
@ -392,9 +392,9 @@ bool PSP_InitStart(const CoreParameter &coreParam, std::string *error_string) {
return false;
}
#if defined(_WIN32) && defined(_M_X64)
#if defined(_WIN32) && PPSSPP_ARCH(AMD64)
INFO_LOG(BOOT, "PPSSPP %s Windows 64 bit", PPSSPP_GIT_VERSION);
#elif defined(_WIN32) && !defined(_M_X64)
#elif defined(_WIN32) && !PPSSPP_ARCH(AMD64)
INFO_LOG(BOOT, "PPSSPP %s Windows 32 bit", PPSSPP_GIT_VERSION);
#else
INFO_LOG(BOOT, "PPSSPP %s", PPSSPP_GIT_VERSION);

2
GPU/Common/VertexDecoderCommon.cpp
View File

@ -1377,7 +1377,7 @@ VertexDecoderJitCache::VertexDecoderJitCache()
AllocCodeSpace(1024 * 64 * 4);
// Add some random code to "help" MSVC's buggy disassembler :(
#if defined(_WIN32) && (defined(_M_IX86) || defined(_M_X64))
#if defined(_WIN32) && (PPSSPP_ARCH(X86) || PPSSPP_ARCH(AMD64))
using namespace Gen;
for (int i = 0; i < 100; i++) {
MOV(32, R(EAX), R(EBX));

21
GPU/Software/Rasterizer.cpp
View File

@ -15,6 +15,7 @@
// Official git repository and contact information can be found at
// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
#include "ppsspp_config.h"
#include <algorithm>
#include <cmath>
@ -39,7 +40,7 @@
namespace Rasterizer {
// Only OK on x64 where our stack is aligned
#if defined(_M_SSE) && !defined(_M_IX86)
#if defined(_M_SSE) && !PPSSPP_ARCH(X86)
static inline __m128 Interpolate(const __m128 &c0, const __m128 &c1, const __m128 &c2, int w0, int w1, int w2, float wsum) {
__m128 v = _mm_mul_ps(c0, _mm_cvtepi32_ps(_mm_set1_epi32(w0)));
v = _mm_add_ps(v, _mm_mul_ps(c1, _mm_cvtepi32_ps(_mm_set1_epi32(w1))));
@ -56,7 +57,7 @@ static inline __m128i Interpolate(const __m128i &c0, const __m128i &c1, const __
// Not sure if that should be regarded as a bug or if casting to float is a valid fix.
static inline Vec4<int> Interpolate(const Vec4<int> &c0, const Vec4<int> &c1, const Vec4<int> &c2, int w0, int w1, int w2, float wsum) {
#if defined(_M_SSE) && !defined(_M_IX86)
#if defined(_M_SSE) && !PPSSPP_ARCH(X86)
return Vec4<int>(Interpolate(c0.ivec, c1.ivec, c2.ivec, w0, w1, w2, wsum));
#else
return ((c0.Cast<float>() * w0 + c1.Cast<float>() * w1 + c2.Cast<float>() * w2) * wsum).Cast<int>();
@ -64,7 +65,7 @@ static inline Vec4<int> Interpolate(const Vec4<int> &c0, const Vec4<int> &c1, co
}
static inline Vec3<int> Interpolate(const Vec3<int> &c0, const Vec3<int> &c1, const Vec3<int> &c2, int w0, int w1, int w2, float wsum) {
#if defined(_M_SSE) && !defined(_M_IX86)
#if defined(_M_SSE) && !PPSSPP_ARCH(X86)
return Vec3<int>(Interpolate(c0.ivec, c1.ivec, c2.ivec, w0, w1, w2, wsum));
#else
return ((c0.Cast<float>() * w0 + c1.Cast<float>() * w1 + c2.Cast<float>() * w2) * wsum).Cast<int>();
@ -72,7 +73,7 @@ static inline Vec3<int> Interpolate(const Vec3<int> &c0, const Vec3<int> &c1, co
}
static inline Vec2<float> Interpolate(const Vec2<float> &c0, const Vec2<float> &c1, const Vec2<float> &c2, int w0, int w1, int w2, float wsum) {
#if defined(_M_SSE) && !defined(_M_IX86)
#if defined(_M_SSE) && !PPSSPP_ARCH(X86)
return Vec2<float>(Interpolate(c0.vec, c1.vec, c2.vec, w0, w1, w2, wsum));
#else
return (c0 * w0 + c1 * w1 + c2 * w2) * wsum;
@ -80,7 +81,7 @@ static inline Vec2<float> Interpolate(const Vec2<float> &c0, const Vec2<float> &
}
static inline Vec4<float> Interpolate(const float &c0, const float &c1, const float &c2, const Vec4<float> &w0, const Vec4<float> &w1, const Vec4<float> &w2, const Vec4<float> &wsum_recip) {
#if defined(_M_SSE) && !defined(_M_IX86)
#if defined(_M_SSE) && !PPSSPP_ARCH(X86)
__m128 v = _mm_mul_ps(w0.vec, _mm_set1_ps(c0));
v = _mm_add_ps(v, _mm_mul_ps(w1.vec, _mm_set1_ps(c1)));
v = _mm_add_ps(v, _mm_mul_ps(w2.vec, _mm_set1_ps(c2)));
@ -1083,7 +1084,7 @@ Vec4<int> TriangleEdge::Start(const ScreenCoords &v0, const ScreenCoords &v1, co
}
inline Vec4<int> TriangleEdge::StepX(const Vec4<int> &w) {
#if defined(_M_SSE) && !defined(_M_IX86)
#if defined(_M_SSE) && !PPSSPP_ARCH(X86)
return _mm_add_epi32(w.ivec, stepX.ivec);
#else
return w + stepX;
@ -1091,7 +1092,7 @@ inline Vec4<int> TriangleEdge::StepX(const Vec4<int> &w) {
}
inline Vec4<int> TriangleEdge::StepY(const Vec4<int> &w) {
#if defined(_M_SSE) && !defined(_M_IX86)
#if defined(_M_SSE) && !PPSSPP_ARCH(X86)
return _mm_add_epi32(w.ivec, stepY.ivec);
#else
return w + stepY;
@ -1099,7 +1100,7 @@ inline Vec4<int> TriangleEdge::StepY(const Vec4<int> &w) {
}
static inline Vec4<int> MakeMask(const Vec4<int> &w0, const Vec4<int> &w1, const Vec4<int> &w2, const Vec4<int> &bias0, const Vec4<int> &bias1, const Vec4<int> &bias2, const Vec4<int> &scissor) {
#if defined(_M_SSE) && !defined(_M_IX86)
#if defined(_M_SSE) && !PPSSPP_ARCH(X86)
__m128i biased0 = _mm_add_epi32(w0.ivec, bias0.ivec);
__m128i biased1 = _mm_add_epi32(w1.ivec, bias1.ivec);
__m128i biased2 = _mm_add_epi32(w2.ivec, bias2.ivec);
@ -1111,7 +1112,7 @@ static inline Vec4<int> MakeMask(const Vec4<int> &w0, const Vec4<int> &w1, const
}
static inline bool AnyMask(const Vec4<int> &mask) {
#if defined(_M_SSE) && !defined(_M_IX86)
#if defined(_M_SSE) && !PPSSPP_ARCH(X86)
// In other words: !(mask.x < 0 && mask.y < 0 && mask.z < 0 && mask.w < 0)
__m128i low2 = _mm_and_si128(mask.ivec, _mm_shuffle_epi32(mask.ivec, _MM_SHUFFLE(3, 2, 3, 2)));
__m128i low1 = _mm_and_si128(low2, _mm_shuffle_epi32(low2, _MM_SHUFFLE(1, 1, 1, 1)));
@ -1123,7 +1124,7 @@ static inline bool AnyMask(const Vec4<int> &mask) {
}
static inline Vec4<float> EdgeRecip(const Vec4<int> &w0, const Vec4<int> &w1, const Vec4<int> &w2) {
#if defined(_M_SSE) && !defined(_M_IX86)
#if defined(_M_SSE) && !PPSSPP_ARCH(X86)
__m128i wsum = _mm_add_epi32(w0.ivec, _mm_add_epi32(w1.ivec, w2.ivec));
// _mm_rcp_ps loses too much precision.
return _mm_div_ps(_mm_set1_ps(1.0f), _mm_cvtepi32_ps(wsum));

7
GPU/Software/Sampler.cpp
View File

@ -89,7 +89,7 @@ SamplerJitCache::SamplerJitCache()
AllocCodeSpace(1024 * 64 * 4);
// Add some random code to "help" MSVC's buggy disassembler :(
#if defined(_WIN32) && (defined(_M_IX86) || defined(_M_X64)) && !PPSSPP_PLATFORM(UWP)
#if defined(_WIN32) && (PPSSPP_ARCH(X86) || PPSSPP_ARCH(AMD64)) && !PPSSPP_PLATFORM(UWP)
using namespace Gen;
for (int i = 0; i < 100; i++) {
MOV(32, R(EAX), R(EBX));
@ -215,7 +215,7 @@ NearestFunc SamplerJitCache::GetNearest(const SamplerID &id) {
Clear();
}
#if defined(_M_X64) && !PPSSPP_PLATFORM(UWP)
#if PPSSPP_ARCH(AMD64) && !PPSSPP_PLATFORM(UWP)
addresses_[id] = GetCodePointer();
NearestFunc func = Compile(id);
cache_[id] = func;
@ -238,8 +238,7 @@ LinearFunc SamplerJitCache::GetLinear(const SamplerID &id) {
Clear();
}
// TODO
#if defined(_M_X64) && !PPSSPP_PLATFORM(UWP)
#if PPSSPP_ARCH(AMD64) && !PPSSPP_PLATFORM(UWP)
addresses_[id] = GetCodePointer();
LinearFunc func = CompileLinear(id);
cache_[id] = (NearestFunc)func;

2
UI/GameSettingsScreen.cpp
View File

@ -977,7 +977,7 @@ void GameSettingsScreen::CreateViews() {
}
#endif
#if defined(_M_X64)
#if PPSSPP_ARCH(AMD64)
systemSettings->Add(new CheckBox(&g_Config.bCacheFullIsoInRam, sy->T("Cache ISO in RAM", "Cache full ISO in RAM")))->SetEnabled(!PSP_IsInited());
#endif

2
Windows/main.cpp
View File

@ -497,7 +497,7 @@ static void WinMainInit() {
#endif
PROFILE_INIT();
#if defined(_M_X64) && defined(_MSC_VER) && _MSC_VER < 1900
#if PPSSPP_ARCH(AMD64) && defined(_MSC_VER) && _MSC_VER < 1900
// FMA3 support in the 2013 CRT is broken on Vista and Windows 7 RTM (fixed in SP1). Just disable it.
_set_FMA3_enable(0);
#endif

3
ext/disarm.cpp
View File

@ -66,6 +66,7 @@
#pragma GCC diagnostic ignored "-Wstring-plus-int"
#endif
#include "ppsspp_config.h"
#include <cstdio>
#include <cstdlib>
#include <cstring>
@ -132,7 +133,7 @@ int GetVm(uint32_t op, bool quad = false, bool dbl = false) {
// Horrible array of hacks but hey. Can be cleaned up later.
bool DisasmVFP(uint32_t op, char *text) {
#if defined(__ANDROID__) && defined(_M_IX86)
#if defined(__ANDROID__) && PPSSPP_ARCH(X86)
// Prevent linking errors with ArmEmitter which I've excluded on x86 android.
strcpy(text, "ARM disasm not available");
#else