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Armjit: Implement CLZ instruction. Disable reg shifts for now (breaks Wipeout Pure).

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This commit is contained in:
Sacha 2013-03-05 14:16:35 +10:00
parent 4a56ebd0a0
commit 4641cf376f
3 changed files with 28 additions and 2 deletions
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5
Common/ArmEmitter.cpp
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@ -542,6 +542,11 @@ void ARMXEmitter::UBFX(ARMReg dest, ARMReg rn, u8 lsb, u8 width)
Write32(condition | (0x7E0 << 16) | ((width - 1) << 16) | (dest << 12) | (lsb << 7) | (5 << 4) | rn);
}
void ARMXEmitter::CLZ(ARMReg rd, ARMReg rm)
{
Write32(condition | (0x16F << 16) | (rd << 12) | (0xF1 << 4) | rm);
}
void ARMXEmitter::BFI(ARMReg rd, ARMReg rn, u8 lsb, u8 width)
{
u32 msb = (lsb + width - 1);

1
Common/ArmEmitter.h
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@ -485,6 +485,7 @@ public:
void SXTAH(ARMReg dest, ARMReg src, ARMReg op2, u8 rotation = 0);
void BFI(ARMReg rd, ARMReg rn, u8 lsb, u8 width);
void UBFX(ARMReg dest, ARMReg op2, u8 lsb, u8 width);
void CLZ(ARMReg rd, ARMReg rm);
// Using just MSR here messes with our defines on the PPC side of stuff (when this code was in dolphin...)
// Just need to put an underscore here, bit annoying.

24
Core/MIPS/ARM/ArmCompALU.cpp
View File

@ -155,8 +155,26 @@ namespace MIPSComp
void Jit::Comp_RType2(u32 op)
{
DISABLE;
}
CONDITIONAL_DISABLE;
int rs = _RS;
int rd = _RD;
// Don't change $zr.
if (rd == 0)
return;
switch (op & 63)
{
case 22: //clz
gpr.MapDirtyIn(rd, rs);
CLZ(gpr.R(rd), gpr.R(rs));
break;
case 23: //clo
DISABLE;
break;
default:
DISABLE;
}
void Jit::Comp_RType3(u32 op)
{
@ -271,6 +289,8 @@ namespace MIPSComp
void Jit::CompShiftVar(u32 op, ArmGen::ShiftType shiftType)
{
// Breaks Wipeout Pure
DISABLE;
int rd = _RD;
int rt = _RT;
int rs = _RS;