diff --git a/Core/MIPS/IR/IRCompVFPU.cpp b/Core/MIPS/IR/IRCompVFPU.cpp
index fab7eaaf03..f2815afc5b 100644
--- a/Core/MIPS/IR/IRCompVFPU.cpp
+++ b/Core/MIPS/IR/IRCompVFPU.cpp
@@ -37,6 +37,7 @@
 // #define CONDITIONAL_DISABLE { Comp_Generic(op); return; }
 #define CONDITIONAL_DISABLE ;
 #define DISABLE { Comp_Generic(op); return; }
+#define INVALIDOP { Comp_Generic(op); return; }
 
 #define _RS MIPS_GET_RS(op)
 #define _RT MIPS_GET_RT(op)
@@ -287,7 +288,7 @@ namespace MIPSComp {
 			break;
 
 		default:
-			DISABLE;
+			INVALIDOP;
 		}
 	}
 
@@ -328,12 +329,11 @@ namespace MIPSComp {
 		case 53: // lvl/lvr.q - highly unusual
 		case 61: // svl/svr.q - highly unusual
 			logBlocks = 1;
-			Comp_Generic(op);
+			DISABLE;
 			break;
 
 		default:
-			DISABLE;
-			break;
+			INVALIDOP;
 		}
 	}
 
@@ -394,7 +394,7 @@ namespace MIPSComp {
 				ir.Write(IROp::SetConstF, dregs[3], ir.AddConstantFloat((vd & 3) == 3 ? 1.0f : 0.0f));
 				break;
 			default:
-				DISABLE;
+				INVALIDOP;
 			}
 		}
 
@@ -440,7 +440,6 @@ namespace MIPSComp {
 			}
 			ir.Write(IROp::Vec4Init, vec[0], (int)init);
 		}
-		return;
 	}
 
 	void IRFrontend::Comp_VHdp(MIPSOpcode op) {
@@ -576,7 +575,7 @@ namespace MIPSComp {
 			case 7: // d[i] = s[i] / t[i]; break; //vdiv
 				break;
 			default:
-				DISABLE;
+				INVALIDOP;
 			}
 			break;
 		case 25: //VFPU1
@@ -584,7 +583,7 @@ namespace MIPSComp {
 			case 0: // d[i] = s[i] * t[i]; break; //vmul
 				break;
 			default:
-				DISABLE;
+				INVALIDOP;
 			}
 			break;
 		case 27: //VFPU3
@@ -598,12 +597,11 @@ namespace MIPSComp {
 				allowSIMD = false;
 				break;
 			default:
-				DISABLE;
+				INVALIDOP;
 			}
 			break;
 		default:
-			DISABLE;
-			break;
+			INVALIDOP;
 		}
 
 		VectorSize sz = GetVecSize(op);
@@ -757,6 +755,8 @@ namespace MIPSComp {
 		// Some can be SIMD'd.
 		switch ((op >> 16) & 0x1f) {
 		case 0:  // vmov
+		case 1:  // vabs
+		case 2:  // vneg
 			canSIMD = true;
 			break;
 		}
@@ -766,6 +766,12 @@ namespace MIPSComp {
 			case 0:  // vmov
 				ir.Write(IROp::Vec4Mov, dregs[0], sregs[0]);
 				break;
+			case 1:  // vabs
+				ir.Write(IROp::Vec4Abs, dregs[0], sregs[0]);
+				break;
+			case 2:  // vneg
+				ir.Write(IROp::Vec4Neg, dregs[0], sregs[0]);
+				break;
 			}
 			ApplyPrefixD(dregs, sz);
 			return;
@@ -823,8 +829,7 @@ namespace MIPSComp {
 				break;
 			case 28: // d[i] = 1.0f / expf(s[i] * (float)M_LOG2E); break; // vrexp2
 			default:
-				DISABLE;
-				break;
+				INVALIDOP;
 			}
 		}
 		for (int i = 0; i < n; i++) {
@@ -921,10 +926,10 @@ namespace MIPSComp {
 						FlushPrefixV();
 						break;
 					}
-					if (imm - 128 < 16) {
+					if (imm - 128 < VFPU_CTRL_MAX) {
 						ir.Write(IROp::VfpuCtrlToReg, rt, imm - 128);
 					} else {
-						DISABLE;
+						INVALIDOP;
 					}
 				}
 			}
@@ -936,7 +941,6 @@ namespace MIPSComp {
 			} else if ((imm - 128) < VFPU_CTRL_MAX) {
 				ir.Write(IROp::SetCtrlVFPU, imm - 128, rt);
 
-				// TODO: Optimization if rt is Imm?
 				if (imm - 128 == VFPU_CTRL_SPREFIX) {
 					js.prefixSFlag = JitState::PREFIX_UNKNOWN;
 				} else if (imm - 128 == VFPU_CTRL_TPREFIX) {
@@ -945,12 +949,12 @@ namespace MIPSComp {
 					js.prefixDFlag = JitState::PREFIX_UNKNOWN;
 				}
 			} else {
-				DISABLE;
+				INVALIDOP;
 			}
 			break;
 
 		default:
-			DISABLE;
+			INVALIDOP;
 		}
 		// This op is marked not to auto-eat prefix so we must do it manually.
 		EatPrefix();
@@ -965,14 +969,10 @@ namespace MIPSComp {
 		int vs = _VS;
 		int imm = op & 0xFF;
 		if (imm >= 128 && imm < 128 + VFPU_CTRL_MAX) {
-			//if (imm - 128 == VFPU_CTRL_CC) {
-			//	gpr.MapReg(MIPS_REG_VFPUCC, 0);
-			//	fp.FMOV(fpr.V(vs), gpr.R(MIPS_REG_VFPUCC));
-			// } else {
 			ir.Write(IROp::VfpuCtrlToReg, IRTEMP_0, imm - 128);
 			ir.Write(IROp::FMovFromGPR, vfpuBase + voffset[vs], IRTEMP_0);
 		} else {
-			DISABLE;
+			INVALIDOP;
 		}
 	}
 
@@ -993,6 +993,8 @@ namespace MIPSComp {
 			} else if (imm - 128 == VFPU_CTRL_DPREFIX) {
 				js.prefixDFlag = JitState::PREFIX_UNKNOWN;
 			}
+		} else {
+			INVALIDOP;
 		}
 	}