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Address a bunch of comments, thanks for the review

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This commit is contained in:
Henrik Rydgard 2016-05-08 21:38:03 +02:00
parent 3eb5480ade
commit 492ea5fac4
10 changed files with 35 additions and 66 deletions
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2
Core/MIPS/ARM64/Arm64Jit.cpp
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@ -284,8 +284,6 @@ const u8 *Arm64Jit::DoJit(u32 em_address, JitBlock *b) {
gpr.Start(analysis);
fpr.Start(analysis);
int partialFlushOffset = 0;
js.numInstructions = 0;
while (js.compiling) {
gpr.SetCompilerPC(GetCompilerPC()); // Let it know for log messages

3
Core/MIPS/IR/IRCompALU.cpp
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@ -192,8 +192,6 @@ void IRJit::CompShiftVar(MIPSOpcode op, IROp shiftOp, IROp shiftOpConst) {
MIPSGPReg rd = _RD;
MIPSGPReg rt = _RT;
MIPSGPReg rs = _RS;
// Not sure if ARM64 wraps like this so let's do it for it. (TODO: According to the ARM ARM, it will indeed mask for us so this is not necessary)
// ANDI2R(SCRATCH1, gpr.R(rs), 0x1F, INVALID_REG);
ir.Write(IROp::AndConst, IRTEMP_0, rs, ir.AddConstant(31));
ir.Write(shiftOp, rd, rt, IRTEMP_0);
}
@ -248,7 +246,6 @@ void IRJit::Comp_Special3(MIPSOpcode op) {
case 0x4: //ins
{
logBlocks = 1;
u32 sourcemask = mask >> pos;
u32 destmask = ~(sourcemask << pos);
ir.Write(IROp::AndConst, IRTEMP_0, rs, ir.AddConstant(sourcemask));

30
Core/MIPS/IR/IRCompBranch.cpp
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@ -53,8 +53,7 @@ namespace MIPSComp
{
using namespace Arm64Gen;
void IRJit::BranchRSRTComp(MIPSOpcode op, IRComparison cc, bool likely)
{
void IRJit::BranchRSRTComp(MIPSOpcode op, IRComparison cc, bool likely) {
if (js.inDelaySlot) {
ERROR_LOG_REPORT(JIT, "Branch in RSRTComp delay slot at %08x in block starting at %08x", GetCompilerPC(), js.blockStart);
return;
@ -67,11 +66,12 @@ void IRJit::BranchRSRTComp(MIPSOpcode op, IRComparison cc, bool likely)
MIPSOpcode delaySlotOp = GetOffsetInstruction(1);
bool delaySlotIsNice = IsDelaySlotNiceReg(op, delaySlotOp, rt, rs);
ir.Write(IROp::Downcount, 0, js.downcountAmount & 0xFF, js.downcountAmount >> 8);
int dcAmount = js.downcountAmount + 1;
ir.Write(IROp::Downcount, 0, dcAmount & 0xFF, dcAmount >> 8);
MIPSGPReg lhs = rs;
MIPSGPReg rhs = rt;
if (!delaySlotIsNice) { // if likely, we don't need this
if (!delaySlotIsNice && !likely) { // if likely, we don't need this
if (rs != 0) {
ir.Write(IROp::Mov, IRTEMP_LHS, rs);
lhs = (MIPSGPReg)IRTEMP_LHS;
@ -109,7 +109,8 @@ void IRJit::BranchRSZeroComp(MIPSOpcode op, IRComparison cc, bool andLink, bool
MIPSOpcode delaySlotOp = GetOffsetInstruction(1);
bool delaySlotIsNice = IsDelaySlotNiceReg(op, delaySlotOp, rs);
ir.Write(IROp::Downcount, 0, js.downcountAmount & 0xFF, js.downcountAmount >> 8);
int dcAmount = js.downcountAmount + 1;
ir.Write(IROp::Downcount, 0, dcAmount & 0xFF, dcAmount >> 8);
MIPSGPReg lhs = rs;
if (!delaySlotIsNice) { // if likely, we don't need this
@ -136,13 +137,13 @@ void IRJit::Comp_RelBranch(MIPSOpcode op) {
// The CC flags here should be opposite of the actual branch becuase they skip the branching action.
switch (op >> 26) {
case 4: BranchRSRTComp(op, IRComparison::NotEqual, false); break;//beq
case 5: BranchRSRTComp(op, IRComparison::Equal, false); break;//bne
case 5: BranchRSRTComp(op, IRComparison::Equal, false); break;//bne
case 6: BranchRSZeroComp(op, IRComparison::Greater, false, false); break;//blez
case 7: BranchRSZeroComp(op, IRComparison::LessEqual, false, false); break;//bgtz
case 20: BranchRSRTComp(op, IRComparison::NotEqual, true); break;//beql
case 21: BranchRSRTComp(op, IRComparison::Equal, true); break;//bnel
case 21: BranchRSRTComp(op, IRComparison::Equal, true); break;//bnel
case 22: BranchRSZeroComp(op, IRComparison::Greater, false, true); break;//blezl
case 23: BranchRSZeroComp(op, IRComparison::LessEqual, false, true); break;//bgtzl
@ -183,7 +184,8 @@ void IRJit::BranchFPFlag(MIPSOpcode op, IRComparison cc, bool likely) {
if (!likely)
CompileDelaySlot();
ir.Write(IROp::Downcount, 0, js.downcountAmount & 0xFF, js.downcountAmount >> 8);
int dcAmount = js.downcountAmount + 1;
ir.Write(IROp::Downcount, 0, dcAmount & 0xFF, dcAmount >> 8);
FlushAll();
// Not taken
@ -221,7 +223,8 @@ void IRJit::BranchVFPUFlag(MIPSOpcode op, IRComparison cc, bool likely) {
logBlocks = 1;
ir.Write(IROp::VfpuCtrlToReg, IRTEMP_LHS, VFPU_CTRL_CC);
ir.Write(IROp::Downcount, 0, js.downcountAmount & 0xFF, js.downcountAmount >> 8);
int dcAmount = js.downcountAmount + 1;
ir.Write(IROp::Downcount, 0, dcAmount & 0xFF, dcAmount >> 8);
// Sometimes there's a VFPU branch in a delay slot (Disgaea 2: Dark Hero Days, Zettai Hero Project, La Pucelle)
// The behavior is undefined - the CPU may take the second branch even if the first one passes.
@ -268,7 +271,8 @@ void IRJit::Comp_Jump(MIPSOpcode op) {
u32 off = _IMM26 << 2;
u32 targetAddr = (GetCompilerPC() & 0xF0000000) | off;
ir.Write(IROp::Downcount, 0, js.downcountAmount & 0xFF, js.downcountAmount >> 8);
int dcAmount = js.downcountAmount + 1;
ir.Write(IROp::Downcount, 0, dcAmount & 0xFF, dcAmount >> 8);
// Might be a stubbed address or something?
if (!Memory::IsValidAddress(targetAddr)) {
@ -316,7 +320,8 @@ void IRJit::Comp_JumpReg(MIPSOpcode op) {
if (andLink && rs == rd)
delaySlotIsNice = false;
ir.Write(IROp::Downcount, 0, js.downcountAmount & 0xFF, js.downcountAmount >> 8);
int dcAmount = js.downcountAmount + 1;
ir.Write(IROp::Downcount, 0, dcAmount & 0xFF, dcAmount >> 8);
int destReg;
if (IsSyscall(delaySlotOp)) {
@ -363,6 +368,9 @@ void IRJit::Comp_Syscall(MIPSOpcode op) {
RestoreRoundingMode();
js.downcountAmount = -offset;
int dcAmount = js.downcountAmount + 1;
ir.Write(IROp::Downcount, 0, dcAmount & 0xFF, dcAmount >> 8);
FlushAll();
ir.Write(IROp::Syscall, 0, ir.AddConstant(op.encoding));

19
Core/MIPS/IR/IRCompFPU.cpp
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@ -80,15 +80,12 @@ void IRJit::Comp_FPULS(MIPSOpcode op) {
switch (op >> 26) {
case 49: //FI(ft) = Memory::Read_U32(addr); break; //lwc1
{
ir.Write(IROp::LoadFloat, ft, rs, ir.AddConstant(offset));
}
break;
break;
case 57: //Memory::Write_U32(FI(ft), addr); break; //swc1
{
ir.Write(IROp::StoreFloat, ft, rs, ir.AddConstant(offset));
}
break;
break;
default:
_dbg_assert_msg_(CPU, 0, "Trying to interpret FPULS instruction that can't be interpreted");
@ -97,7 +94,7 @@ void IRJit::Comp_FPULS(MIPSOpcode op) {
}
void IRJit::Comp_FPUComp(MIPSOpcode op) {
DISABLE;
DISABLE; // IROps not yet implemented
int opc = op & 0xF;
if (opc >= 8) opc -= 8; // alias
@ -195,8 +192,7 @@ void IRJit::Comp_FPU2op(MIPSOpcode op) {
}
}
void IRJit::Comp_mxc1(MIPSOpcode op)
{
void IRJit::Comp_mxc1(MIPSOpcode op) {
CONDITIONAL_DISABLE;
int fs = _FS;
@ -215,9 +211,8 @@ void IRJit::Comp_mxc1(MIPSOpcode op)
return;
}
if (fs == 31) {
DISABLE;
}
else if (fs == 0) {
DISABLE; // TODO: Add a new op
} else if (fs == 0) {
ir.Write(IROp::SetConst, rt, ir.AddConstant(MIPSState::FCR0_VALUE));
} else {
// Unsupported regs are always 0.

10
Core/MIPS/IR/IRInst.h
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@ -219,16 +219,6 @@ enum {
IRREG_FPCOND = 229
};
enum class IRParam {
Ignore = '_',
UImm8 = 'U',
Const = 'C',
GPR = 'G',
FPR = 'F',
VPR = 'V',
VCtrl = 'T',
};
struct IRMeta {
IROp op;
const char *name;

25
Core/MIPS/IR/IRJit.cpp
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@ -39,8 +39,7 @@
#include "Core/MIPS/IR/IRPassSimplify.h"
#include "Core/MIPS/JitCommon/JitCommon.h"
namespace MIPSComp
{
namespace MIPSComp {
IRJit::IRJit(MIPSState *mips) : mips_(mips) {
logBlocks = 0;
@ -48,8 +47,7 @@ IRJit::IRJit(MIPSState *mips) : mips_(mips) {
js.startDefaultPrefix = mips_->HasDefaultPrefix();
js.currentRoundingFunc = convertS0ToSCRATCH1[0];
u32 size = 128 * 1024;
blTrampolines_ = kernelMemory.Alloc(size, true, "trampoline");
logBlocks = 12;
// blTrampolines_ = kernelMemory.Alloc(size, true, "trampoline");
InitIR();
}
@ -110,7 +108,7 @@ void IRJit::FlushPrefixV() {
}
void IRJit::ClearCache() {
ILOG("ARM64Jit: Clearing the cache!");
ILOG("IRJit: Clearing the cache!");
blocks_.Clear();
}
@ -184,12 +182,6 @@ void IRJit::RunLoopUntil(u64 globalticks) {
// ApplyRoundingMode(true);
// IR Dispatcher
FILE *f;
int numBlocks = 0;
if (numBlocks) {
f = fopen("E:\\blockir.txt", "w");
}
while (true) {
// RestoreRoundingMode(true);
CoreTiming::Advance();
@ -203,18 +195,9 @@ void IRJit::RunLoopUntil(u64 globalticks) {
u32 data = inst & 0xFFFFFF;
if (opcode == (MIPS_EMUHACK_OPCODE >> 24)) {
IRBlock *block = blocks_.GetBlock(data);
if (numBlocks > 0) {
// ILOG("Run block at %08x : v1=%08x a0=%08x", mips_->pc, mips_->r[MIPS_REG_V1], mips_->r[MIPS_REG_A0]);
fprintf(f, "BLOCK : %08x v0: %08x v1: %08x a0: %08x s0: %08x s4: %08x\n", mips_->pc, mips_->r[MIPS_REG_V0], mips_->r[MIPS_REG_V1], mips_->r[MIPS_REG_A0], mips_->r[MIPS_REG_S0], mips_->r[MIPS_REG_S4]);
fflush(f);
numBlocks--;
}
mips_->pc = IRInterpret(mips_, block->GetInstructions(), block->GetConstants(), block->GetNumInstructions());
} else {
if (mips_->pc == 0x0880de94)
logBlocks = 10;
// RestoreRoundingMode(true);
// ILOG("Compile block at %08x : v1=%08x a0=%08x", mips_->pc, mips_->r[MIPS_REG_V1], mips_->r[MIPS_REG_A0]);
Compile(mips_->pc);
// ApplyRoundingMode(true);
}
@ -246,8 +229,6 @@ void IRJit::DoJit(u32 em_address, IRBlock *b) {
js.PrefixStart();
ir.Clear();
int partialFlushOffset = 0;
js.numInstructions = 0;
while (js.compiling) {
MIPSOpcode inst = Memory::Read_Opcode_JIT(GetCompilerPC());

6
Core/MIPS/IR/IRJit.h
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@ -265,9 +265,9 @@ private:
IRWriter ir;
// where to write branch-likely trampolines
u32 blTrampolines_;
int blTrampolineCount_;
// where to write branch-likely trampolines. not used atm
// u32 blTrampolines_;
// int blTrampolineCount_;
public:
// Code pointers

2
Core/MIPS/JitCommon/JitCommon.cpp
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@ -50,7 +50,7 @@ namespace MIPSComp {
#if defined(ARM)
return new MIPSComp::ArmJit(mips);
#elif defined(ARM64)
return new MIPSComp::IRJit(mips);
return new MIPSComp::Arm64Jit(mips);
#elif defined(_M_IX86) || defined(_M_X64)
return new MIPSComp::Jit(mips);
#elif defined(MIPS)

2
Core/MIPS/x86/Asm.cpp
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@ -40,7 +40,7 @@ namespace MIPSComp
//TODO - make an option
//#if _DEBUG
static bool enableDebug = true;
static bool enableDebug = false;
//#else
// bool enableDebug = false;

2
Core/MemMapFunctions.cpp
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@ -87,7 +87,7 @@ inline void ReadFromHardware(T &var, const u32 address) {
var = *((const T*)GetPointerUnchecked(address));
} else {
// In jit, we only flush PC when bIgnoreBadMemAccess is off.
if (g_Config.iCpuCore != CPU_CORE_INTERPRETER && g_Config.bIgnoreBadMemAccess) {
if (g_Config.iCpuCore == CPU_CORE_JIT && g_Config.bIgnoreBadMemAccess) {
WARN_LOG(MEMMAP, "ReadFromHardware: Invalid address %08x", address);
} else {
WARN_LOG(MEMMAP, "ReadFromHardware: Invalid address %08x PC %08x LR %08x", address, currentMIPS->pc, currentMIPS->r[MIPS_REG_RA]);