diff --git a/Common/CPUDetect.cpp b/Common/CPUDetect.cpp
index 2efdca438c..ac5cd2e640 100644
--- a/Common/CPUDetect.cpp
+++ b/Common/CPUDetect.cpp
@@ -224,6 +224,11 @@ void CPUInfo::Detect() {
 			}
 		}
 
+
+		// TSX support require check:
+		// -- Is the RTM bit set in CPUID? (>>11)
+		// -- No need to check HLE bit because legacy processors ignore HLE hints
+		// -- See https://software.intel.com/en-us/articles/how-to-detect-new-instruction-support-in-the-4th-generation-intel-core-processor-family
 		if (max_std_fn >= 7)
 		{
 			do_cpuid(cpu_id, 0x00000007);
@@ -236,6 +241,8 @@ void CPUInfo::Detect() {
 				bBMI2 = true;
 			if ((cpu_id[1] >> 29) & 1)
 				bSHA = true;
+			if ((cpu_id[1] >> 11) & 1)
+				bRTM = true;
 		}
 	}
 	if (max_ex_fn >= 0x80000004) {
@@ -419,6 +426,7 @@ std::string CPUInfo::Summarize()
 	if (bAES) sum += ", AES";
 	if (bSHA) sum += ", SHA";
 	if (bXOP) sum += ", XOP";
+	if (bRTM) sum += ", TSX";
 	if (bLongMode) sum += ", 64-bit support";
 	return sum;
 }
diff --git a/Common/CPUDetect.h b/Common/CPUDetect.h
index d0cc37837c..1318814070 100644
--- a/Common/CPUDetect.h
+++ b/Common/CPUDetect.h
@@ -52,6 +52,7 @@ struct CPUInfo {
 	bool bBMI1;
 	bool bBMI2;
 	bool bXOP;
+	bool bRTM;
 
 	// x86 : SIMD 128 bit
 	bool bSSE;