Fix Sonic's ArmEmitter changes. FastMem should work now.

This commit is contained in:
Sacha 2013-03-15 11:26:56 +10:00
parent 7d89b12823
commit 5091c7aae2
2 changed files with 7 additions and 7 deletions

View File

@ -139,8 +139,10 @@ void CPUInfo::Detect()
bVFPv3 = CheckCPUFeature("vfpv3");
bTLS = CheckCPUFeature("tls");
bVFPv4 = CheckCPUFeature("vfpv4");
bIDIVa = CheckCPUFeature("idiva");
bIDIVt = CheckCPUFeature("idivt");
// On some buggy kernels(Qualcomm) they show that they support VFPv4 but not IDIVa
// All VFPv4 CPUs will support IDIVa
bIDIVa = bVFPv4 || CheckCPUFeature("idiva");
bIDIVt = bVFPv4 || CheckCPUFeature("idivt");
// These two require ARMv8 or higher
bFP = CheckCPUFeature("fp");
bASIMD = CheckCPUFeature("asimd");
@ -200,10 +202,8 @@ std::string CPUInfo::Summarize()
if (bVFPv3) sum += ", VFPv3";
if (bTLS) sum += ", TLS";
if (bVFPv4) sum += ", VFPv4";
// On some buggy kernels(Qualcomm) they show that they support VFPv4 but not IDIVa
// All VFPv4 CPUs will support IDIVa
if (bIDIVa || bVFPv4) sum += ", IDIVa";
if (bIDIVt || bVFPv4) sum += ", IDIVt";
if (bIDIVa) sum += ", IDIVa";
if (bIDIVt) sum += ", IDIVt";
return sum;
}

View File

@ -705,8 +705,8 @@ void ARMXEmitter::WriteStoreOp(u32 Op, ARMReg Rt, ARMReg Rn, Operand2 Rm, bool R
{
Data = Rm.GetData();
Add = RegAdd;
break;
}
break;
default:
// RSR not supported for any of these
// We already have the warning above