mirror of
https://github.com/hrydgard/ppsspp.git
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Merge pull request #1266 from unknownbrackets/armjit-minor
Updates to ArmEmitter from Dolphin
This commit is contained in:
Henrik Rydgård
commit
58f8b8c7a1
@ -221,7 +221,7 @@ void ARMXEmitter::MOVI2R(ARMReg reg, u32 val, bool optimize)
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{
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Operand2 op2;
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bool inverse;
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if (cpu_info.bArmV7 && !optimize)
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{
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// For backpatching on ARMv7
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@ -667,7 +667,6 @@ void ARMXEmitter::MRS (ARMReg dest)
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{
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Write32(condition | (16 << 20) | (15 << 16) | (dest << 12));
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}
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void ARMXEmitter::LDREX(ARMReg dest, ARMReg base)
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{
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Write32(condition | (25 << 20) | (base << 16) | (dest << 12) | 0xF9F);
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@ -685,6 +684,7 @@ void ARMXEmitter::SVC(Operand2 op)
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{
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Write32(condition | (0x0F << 24) | op.Imm24());
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}
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// IMM, REG, IMMSREG, RSR
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// -1 for invalid if the instruction doesn't support that
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const s32 LoadStoreOps[][4] = {
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@ -883,18 +883,126 @@ void ARMXEmitter::VSUB(IntegerSize Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
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}
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// VFP Specific
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void ARMXEmitter::VLDR(ARMReg Dest, ARMReg Base, u16 offset)
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struct VFPEnc
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{
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_assert_msg_(DYNA_REC, Dest >= S0 && Dest <= D31, "Passed Invalid dest register to VLDR");
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s16 opc1;
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s16 opc2;
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};
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// Double/single, Neon
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const VFPEnc VFPOps[][2] = {
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{{0xE0, 0xA0}, {0x20, 0xD1}}, // 0: VMLA
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{{0xE0, 0xA4}, {0x22, 0xD1}}, // 1: VMLS
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{{0xE3, 0xA0}, {0x20, 0xD0}}, // 2: VADD
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{{0xE3, 0xA4}, {0x22, 0xD0}}, // 3: VSUB
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{{0xE2, 0xA0}, {0x30, 0xD1}}, // 4: VMUL
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{{0xEB, 0xAC}, { -1 /* 0x3B */, -1 /* 0x70 */}}, // 5: VABS(Vn(0x0) used for encoding)
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{{0xE8, 0xA0}, { -1, -1}}, // 6: VDIV
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{{0xEB, 0xA4}, { -1 /* 0x3B */, -1 /* 0x78 */}}, // 7: VNEG(Vn(0x1) used for encoding)
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{{0xEB, 0xAC}, { -1, -1}}, // 8: VSQRT (Vn(0x1) used for encoding)
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{{0xEB, 0xA4}, { -1, -1}}, // 9: VCMP (Vn(0x4 | #0 ? 1 : 0) used for encoding)
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{{0xEB, 0xAC}, { -1, -1}}, // 10: VCMPE (Vn(0x4 | #0 ? 1 : 0) used for encoding)
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{{ -1, -1}, {0x3B, 0x30}}, // 11: VABSi
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};
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const char *VFPOpNames[] = {
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"VMLA",
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"VMLS",
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"VADD",
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"VSUB",
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"VMUL",
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"VABS",
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"VDIV",
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"VNEG",
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"VSQRT",
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"VCMP",
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"VCMPE",
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"VABSi",
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};
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u32 ARMXEmitter::EncodeVd(ARMReg Vd)
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{
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bool quad_reg = Vd >= Q0;
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bool double_reg = Vd >= D0;
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ARMReg Reg = SubBase(Vd);
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if (quad_reg)
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return ((Reg & 0x10) << 18) | ((Reg & 0xF) << 12);
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else
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if (double_reg)
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return ((Reg & 0x10) << 18) | ((Reg & 0xF) << 12);
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else
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return ((Reg & 0x1) << 22) | ((Reg & 0x1E) << 11);
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}
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u32 ARMXEmitter::EncodeVn(ARMReg Vn)
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{
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bool quad_reg = Vn >= Q0;
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bool double_reg = Vn >= D0;
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ARMReg Reg = SubBase(Vn);
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if (quad_reg)
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return ((Reg & 0xF) << 16) | ((Reg & 0x10) << 3);
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else
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if (double_reg)
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return ((Reg & 0xF) << 16) | ((Reg & 0x10) << 3);
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else
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return ((Reg & 0x1E) << 15) | ((Reg & 0x1) << 7);
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}
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u32 ARMXEmitter::EncodeVm(ARMReg Vm)
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{
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bool quad_reg = Vm >= Q0;
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bool double_reg = Vm >= D0;
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ARMReg Reg = SubBase(Vm);
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if (quad_reg)
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return ((Reg & 0x10) << 2) | (Reg & 0xF);
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else
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if (double_reg)
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return ((Reg & 0x10) << 2) | (Reg & 0xF);
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else
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return ((Reg & 0x1) << 5) | (Reg >> 1);
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}
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void ARMXEmitter::WriteVFPDataOp(u32 Op, ARMReg Vd, ARMReg Vn, ARMReg Vm)
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{
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bool quad_reg = Vd >= Q0;
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bool double_reg = Vd >= D0 && Vd < Q0;
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VFPEnc enc = VFPOps[Op][quad_reg];
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if (enc.opc1 == -1 && enc.opc2 == -1)
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_assert_msg_(DYNA_REC, false, "%s does not support %s", VFPOpNames[Op], quad_reg ? "NEON" : "VFP");
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u32 VdEnc = EncodeVd(Vd);
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u32 VnEnc = EncodeVn(Vn);
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u32 VmEnc = EncodeVm(Vm);
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u32 cond = quad_reg ? (0xF << 28) : condition;
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Write32(cond | (enc.opc1 << 20) | VnEnc | VdEnc | (enc.opc2 << 4) | (quad_reg << 6) | (double_reg << 8) | VmEnc);
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}
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void ARMXEmitter::VMLA(ARMReg Vd, ARMReg Vn, ARMReg Vm){ WriteVFPDataOp(0, Vd, Vn, Vm); }
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void ARMXEmitter::VMLS(ARMReg Vd, ARMReg Vn, ARMReg Vm){ WriteVFPDataOp(1, Vd, Vn, Vm); }
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void ARMXEmitter::VADD(ARMReg Vd, ARMReg Vn, ARMReg Vm){ WriteVFPDataOp(2, Vd, Vn, Vm); }
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void ARMXEmitter::VSUB(ARMReg Vd, ARMReg Vn, ARMReg Vm){ WriteVFPDataOp(3, Vd, Vn, Vm); }
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void ARMXEmitter::VMUL(ARMReg Vd, ARMReg Vn, ARMReg Vm){ WriteVFPDataOp(4, Vd, Vn, Vm); }
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void ARMXEmitter::VABS(ARMReg Vd, ARMReg Vm){ WriteVFPDataOp(5, Vd, D0, Vm); }
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void ARMXEmitter::VDIV(ARMReg Vd, ARMReg Vn, ARMReg Vm){ WriteVFPDataOp(6, Vd, Vn, Vm); }
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void ARMXEmitter::VNEG(ARMReg Vd, ARMReg Vm){ WriteVFPDataOp(7, Vd, D1, Vm); }
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void ARMXEmitter::VSQRT(ARMReg Vd, ARMReg Vm){ WriteVFPDataOp(8, Vd, D1, Vm); }
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void ARMXEmitter::VCMP(ARMReg Vd, ARMReg Vm){ WriteVFPDataOp(9, Vd, D4, Vm); }
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void ARMXEmitter::VCMPE(ARMReg Vd, ARMReg Vm){ WriteVFPDataOp(10, Vd, D4, Vm); }
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void ARMXEmitter::VCMP(ARMReg Vd){ WriteVFPDataOp(9, Vd, D5, D0); }
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void ARMXEmitter::VCMPE(ARMReg Vd){ WriteVFPDataOp(10, Vd, D5, D0); }
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void ARMXEmitter::VLDR(ARMReg Dest, ARMReg Base, s16 offset)
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{
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_assert_msg_(DYNA_REC, Dest >= S0 && Dest <= D31, "Passed Invalid dest register to VLDR");
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_assert_msg_(DYNA_REC, Base <= R15, "Passed invalid Base register to VLDR");
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_assert_msg_(DYNA_REC, (offset & 0xC03) == 0, "VLDR: Offset needs to be word aligned and small enough");
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if (offset & 0xC03) {
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ERROR_LOG(DYNA_REC, "VLDR: Bad offset %08x", offset);
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}
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bool Add = offset >= 0 ? true : false;
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u32 imm = abs(offset);
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// ERROR_LOG(DYNA_REC, "VLDR: s%i, r%i + %i", Dest - S0, Base, offset);
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_assert_msg_(DYNA_REC, (imm & 0xC03) == 0, "VLDR: Offset needs to be word aligned and small enough");
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if (imm & 0xC03)
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ERROR_LOG(DYNA_REC, "VLDR: Bad offset %08x", imm);
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bool single_reg = Dest < D0;
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@ -902,26 +1010,27 @@ void ARMXEmitter::VLDR(ARMReg Dest, ARMReg Base, u16 offset)
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if (single_reg)
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{
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Write32(condition | (0x1B << 23) | ((Dest & 0x1) << 22) | (1 << 20) | (Base << 16) \
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| ((Dest & 0x1E) << 11) | (10 << 8) | (offset >> 2));
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Write32(condition | (0xD << 24) | (Add << 23) | ((Dest & 0x1) << 22) | (1 << 20) | (Base << 16) \
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| ((Dest & 0x1E) << 11) | (10 << 8) | (imm >> 2));
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}
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else
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{
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Write32(condition | (0x1B << 23) | ((Dest & 0x10) << 18) | (1 << 20) | (Base << 16) \
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| ((Dest & 0xF) << 12) | (11 << 8) | (offset >> 2));
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Write32(condition | (0xD << 24) | (Add << 23) | ((Dest & 0x10) << 18) | (1 << 20) | (Base << 16) \
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| ((Dest & 0xF) << 12) | (11 << 8) | (imm >> 2));
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}
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}
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void ARMXEmitter::VSTR(ARMReg Src, ARMReg Base, u16 offset)
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void ARMXEmitter::VSTR(ARMReg Src, ARMReg Base, s16 offset)
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{
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_assert_msg_(DYNA_REC, Src >= S0 && Src <= D31, "Passed invalid src register to VSTR");
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_assert_msg_(DYNA_REC, Base <= R15, "Passed invalid base register to VSTR");
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_assert_msg_(DYNA_REC, (offset & 0xC03) == 0, "VSTR: Offset needs to be word aligned");
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if (offset & 0xC03) {
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ERROR_LOG(DYNA_REC, "VSTR: Bad offset %08x", offset);
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}
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// ERROR_LOG(DYNA_REC, "VSTR: s%i, r%i + %i", Src - S0, Base, offset);
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bool Add = offset >= 0 ? true : false;
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u32 imm = abs(offset);
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_assert_msg_(DYNA_REC, (imm & 0xC03) == 0, "VSTR: Offset needs to be word aligned and small enough");
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if (imm & 0xC03)
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ERROR_LOG(DYNA_REC, "VSTR: Bad offset %08x", imm);
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bool single_reg = Src < D0;
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@ -929,51 +1038,13 @@ void ARMXEmitter::VSTR(ARMReg Src, ARMReg Base, u16 offset)
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if (single_reg)
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{
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Write32(condition | (0x1B << 23) | ((Src & 0x1) << 22) | (Base << 16) \
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| ((Src & 0x1E) << 11) | (10 << 8) | (offset >> 2));
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Write32(condition | (0xD << 24) | (Add << 23) | ((Src & 0x1) << 22) | (Base << 16) \
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| ((Src & 0x1E) << 11) | (10 << 8) | (imm >> 2));
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}
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else
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{
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Write32(condition | (0x1B << 23) | ((Src & 0x10) << 18) | (Base << 16) \
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| ((Src & 0xF) << 12) | (11 << 8) | (offset >> 2));
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}
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}
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void ARMXEmitter::VCMP(ARMReg Vd, ARMReg Vm, bool E)
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{
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_assert_msg_(DYNA_REC, Vd < Q0, "Passed invalid Vd to VCMP");
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bool single_reg = Vd < D0;
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Vd = SubBase(Vd);
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Vm = SubBase(Vm);
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if (single_reg)
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{
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Write32(condition | (0x1D << 23) | ((Vd & 0x1) << 22) | (0x34 << 16) | ((Vd & 0x1E) << 11) \
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| (E << 7) | (0x29 << 6) | ((Vm & 0x1) << 5) | (Vm >> 1));
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}
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else
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{
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Write32(condition | (0x1D << 23) | ((Vd & 0x10) << 18) | (0x34 << 16) | ((Vd & 0xF) << 12) \
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| (E << 7) | (0x2C << 6) | ((Vm & 0x10) << 1) | (Vm & 0xF));
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}
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}
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void ARMXEmitter::VCMP(ARMReg Vd, bool E)
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{
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_assert_msg_(DYNA_REC, Vd < Q0, "Passed invalid Vd to VCMP");
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bool single_reg = Vd < D0;
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Vd = SubBase(Vd);
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if (single_reg)
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{
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Write32(condition | (0x1D << 23) | ((Vd & 0x1) << 22) | (0x35 << 16) | ((Vd & 0x1E) << 11) \
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| (E << 7) | (0x29 << 6));
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}
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else
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{
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Write32(condition | (0x1D << 23) | ((Vd & 0x10) << 18) | (0x35 << 16) | ((Vd & 0xF) << 12) \
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| (E << 7) | (0x2C << 6));
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Write32(condition | (0xD << 24) | (Add << 23) | ((Src & 0x10) << 18) | (Base << 16) \
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| ((Src & 0xF) << 12) | (11 << 8) | (imm >> 2));
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}
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}
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@ -987,218 +1058,7 @@ void ARMXEmitter::VMSR(ARMReg Rt) {
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Write32(condition | (0xEE << 20) | (1 << 16) | (Rt << 12) | 0xA10);
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}
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void ARMXEmitter::VDIV(ARMReg Vd, ARMReg Vn, ARMReg Vm)
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{
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_assert_msg_(DYNA_REC, Vd < Q0, "Pased invalid dest register to VSQRT");
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_assert_msg_(DYNA_REC, Vn < Q0, "Passed invalid Vn to VSQRT");
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_assert_msg_(DYNA_REC, Vm < Q0, "Passed invalid Vm to VSQRT");
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bool single_reg = Vd < D0;
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Vd = SubBase(Vd);
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Vn = SubBase(Vn);
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Vm = SubBase(Vm);
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if (single_reg)
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{
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Write32(condition | (0x1D << 23) | ((Vd & 0x1) << 22) | ((Vn & 0x1E) << 15) \
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| ((Vd & 0x1E) << 11) | (0xA << 8) | ((Vn & 0x1) << 7) | ((Vm & 0x1) << 5) \
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| (Vm >> 1));
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}
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else
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{
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Write32(condition | (0x1D << 23) | ((Vd & 0x10) << 18) | ((Vn & 0xF) << 16) \
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| ((Vd & 0xF) << 12) | (0xB << 8) | ((Vn & 0x10) << 3) | ((Vm & 0x10) << 2) \
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| (Vm & 0xF));
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}
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}
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void ARMXEmitter::VSQRT(ARMReg Vd, ARMReg Vm)
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{
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_assert_msg_(DYNA_REC, Vd < Q0, "Pased invalid dest register to VSQRT");
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_assert_msg_(DYNA_REC, Vm < Q0, "Passed invalid Vm to VSQRT");
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bool single_reg = Vd < D0;
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Vd = SubBase(Vd);
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Vm = SubBase(Vm);
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if (single_reg)
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{
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Write32(condition | (0x1D << 23) | ((Vd & 0x1) << 22) | (0x31 << 16) \
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| ((Vd & 0x1E) << 11) | (0x2B << 6) | ((Vm & 0x1) << 5) | (Vm >> 1));
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}
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else
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{
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Write32(condition | (0x1D << 23) | ((Vd & 0x10) << 18) | (0x31 << 16) \
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| ((Vd & 0xF) << 12) | (0x2F << 6) | ((Vm & 0x10) << 2) | (Vm & 0xF));
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}
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}
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// VFP and ASIMD
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void ARMXEmitter::VADD(ARMReg Vd, ARMReg Vn, ARMReg Vm)
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{
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_assert_msg_(DYNA_REC, Vd >= S0, "Passed invalid dest register to VADD");
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_assert_msg_(DYNA_REC, Vn >= S0, "Passed invalid Vn to VADD");
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_assert_msg_(DYNA_REC, Vm >= S0, "Passed invalid Vm to VADD");
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bool single_reg = Vd < D0;
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bool double_reg = Vd < Q0;
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Vd = SubBase(Vd);
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Vn = SubBase(Vn);
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Vm = SubBase(Vm);
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if (single_reg)
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{
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Write32(condition | (0x1C << 23) | ((Vd & 0x1) << 22) | (0x3 << 20) \
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| ((Vn & 0x1E) << 15) | ((Vd & 0x1E) << 11) | (0x5 << 9) \
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| ((Vn & 0x1) << 7) | ((Vm & 0x1) << 5) | (Vm >> 1));
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}
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else
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{
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if (double_reg)
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{
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Write32(condition | (0x1C << 23) | ((Vd & 0x10) << 18) | (0x3 << 20) \
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| ((Vn & 0xF) << 16) | ((Vd & 0xF) << 12) | (0xB << 8) \
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| ((Vn & 0x10) << 3) | ((Vm & 0x10) << 2) | (Vm & 0xF));
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}
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else
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{
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_assert_msg_(DYNA_REC, cpu_info.bNEON, "Trying to use VADD with Quad Reg without support!");
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Write32((0xF2 << 24) | ((Vd & 0x10) << 18) | ((Vn & 0xF) << 16) \
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| ((Vd & 0xF) << 12) | (0xD << 8) | ((Vn & 0x10) << 3) \
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| (1 << 6) | ((Vm & 0x10) << 2) | (Vm & 0xF));
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}
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}
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}
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void ARMXEmitter::VSUB(ARMReg Vd, ARMReg Vn, ARMReg Vm)
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{
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_assert_msg_(DYNA_REC, Vd >= S0, "Passed invalid dest register to VSUB");
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_assert_msg_(DYNA_REC, Vn >= S0, "Passed invalid Vn to VSUB");
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_assert_msg_(DYNA_REC, Vm >= S0, "Passed invalid Vm to VSUB");
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bool single_reg = Vd < D0;
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bool double_reg = Vd < Q0;
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Vd = SubBase(Vd);
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Vn = SubBase(Vn);
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Vm = SubBase(Vm);
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if (single_reg)
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{
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Write32(condition | (0x1C << 23) | ((Vd & 0x1) << 22) | (0x3 << 20) \
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| ((Vn & 0x1E) << 15) | ((Vd & 0x1E) << 11) | (0x5 << 9) \
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| ((Vn & 0x1) << 7) | (1 << 6) | ((Vm & 0x1) << 5) | (Vm >> 1));
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}
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else
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{
|
||||
if (double_reg)
|
||||
{
|
||||
Write32(condition | (0x1C << 23) | ((Vd & 0x10) << 18) | (0x3 << 20) \
|
||||
| ((Vn & 0xF) << 16) | ((Vd & 0xF) << 12) | (0xB << 8) \
|
||||
| ((Vn & 0x10) << 3) | (1 << 6) | ((Vm & 0x10) << 2) | (Vm & 0xF));
|
||||
}
|
||||
else
|
||||
{
|
||||
_assert_msg_(DYNA_REC, cpu_info.bNEON, "Trying to use VADD with Quad Reg without support!");
|
||||
Write32((0xF2 << 24) | (1 << 21) | ((Vd & 0x10) << 18) | ((Vn & 0xF) << 16) \
|
||||
| ((Vd & 0xF) << 12) | (0xD << 8) | ((Vn & 0x10) << 3) \
|
||||
| (1 << 6) | ((Vm & 0x10) << 2) | (Vm & 0xF));
|
||||
}
|
||||
}
|
||||
}
|
||||
// VFP and ASIMD
|
||||
void ARMXEmitter::VMUL(ARMReg Vd, ARMReg Vn, ARMReg Vm)
|
||||
{
|
||||
_assert_msg_(DYNA_REC, Vd >= S0, "Passed invalid dest register to VADD");
|
||||
_assert_msg_(DYNA_REC, Vn >= S0, "Passed invalid Vn to VADD");
|
||||
_assert_msg_(DYNA_REC, Vm >= S0, "Passed invalid Vm to VADD");
|
||||
bool single_reg = Vd < D0;
|
||||
bool double_reg = Vd < Q0;
|
||||
|
||||
Vd = SubBase(Vd);
|
||||
Vn = SubBase(Vn);
|
||||
Vm = SubBase(Vm);
|
||||
|
||||
if (single_reg)
|
||||
{
|
||||
Write32(condition | (0x1C << 23) | ((Vd & 0x1) << 22) | (0x2 << 20) \
|
||||
| ((Vn & 0x1E) << 15) | ((Vd & 0x1E) << 11) | (0x5 << 9) \
|
||||
| ((Vn & 0x1) << 7) | ((Vm & 0x1) << 5) | (Vm >> 1));
|
||||
}
|
||||
else
|
||||
{
|
||||
if (double_reg)
|
||||
{
|
||||
Write32(condition | (0x1C << 23) | ((Vd & 0x10) << 18) | (0x2 << 20) \
|
||||
| ((Vn & 0xF) << 16) | ((Vd & 0xF) << 12) | (0xB << 8) \
|
||||
| ((Vn & 0x10) << 3) | ((Vm & 0x10) << 2) | (Vm & 0xF));
|
||||
}
|
||||
else
|
||||
{
|
||||
_assert_msg_(DYNA_REC, cpu_info.bNEON, "Trying to use VMUL with Quad Reg without support!");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void ARMXEmitter::VMLA(ARMReg Vd, ARMReg Vn, ARMReg Vm)
|
||||
{
|
||||
_assert_msg_(DYNA_REC, Vd >= S0, "Passed invalid dest register to VMLA");
|
||||
_assert_msg_(DYNA_REC, Vn >= S0, "Passed invalid Vn to VMLA");
|
||||
_assert_msg_(DYNA_REC, Vm >= S0, "Passed invalid Vm to VMLA");
|
||||
bool single_reg = Vd < D0;
|
||||
bool double_reg = Vd < Q0;
|
||||
|
||||
Vd = SubBase(Vd);
|
||||
Vn = SubBase(Vn);
|
||||
Vm = SubBase(Vm);
|
||||
|
||||
if (single_reg)
|
||||
{
|
||||
Write32(condition | (0x1C << 23) | ((Vd & 0x1) << 22) | (0x0 << 20) \
|
||||
| ((Vn & 0x1E) << 15) | ((Vd & 0x1E) << 11) | (0x5 << 9) \
|
||||
| ((Vn & 0x1) << 7) | ((Vm & 0x1) << 5) | (Vm >> 1));
|
||||
}
|
||||
else
|
||||
{
|
||||
_assert_msg_(DYNA_REC, false, "VMLA: Please implement!");
|
||||
}
|
||||
}
|
||||
|
||||
void ARMXEmitter::VABS(ARMReg Vd, ARMReg Vm)
|
||||
{
|
||||
bool single_reg = Vd < D0;
|
||||
|
||||
Vd = SubBase(Vd);
|
||||
Vm = SubBase(Vm);
|
||||
|
||||
if (single_reg)
|
||||
{
|
||||
Write32(condition | (0x1D << 23) | ((Vd & 0x1) << 22) | (0x30 << 16) \
|
||||
| ((Vd & 0x1E) << 11) | (0x2B << 6) | ((Vm & 0x1) << 5) | (Vm >> 1));
|
||||
}
|
||||
else
|
||||
{
|
||||
Write32(condition | (0x1D << 23) | ((Vd & 0x10) << 18) | (0x30 << 16) \
|
||||
| ((Vd & 0xF) << 12) | (0x2F << 6) | ((Vm & 0x10) << 2) | (Vm & 0xF));
|
||||
}
|
||||
}
|
||||
|
||||
void ARMXEmitter::VNEG(ARMReg Vd, ARMReg Vm)
|
||||
{
|
||||
bool single_reg = Vd < D0;
|
||||
|
||||
Vd = SubBase(Vd);
|
||||
Vm = SubBase(Vm);
|
||||
|
||||
if (single_reg)
|
||||
{
|
||||
Write32(condition | (0x1D << 23) | ((Vd & 0x1) << 22) | (0x31 << 16) \
|
||||
| ((Vd & 0x1E) << 11) | (0x29 << 6) | ((Vm & 0x1) << 5) | (Vm >> 1));
|
||||
}
|
||||
else
|
||||
{
|
||||
Write32(condition | (0x1D << 23) | ((Vd & 0x10) << 18) | (0x31 << 16) \
|
||||
| ((Vd & 0xF) << 12) | (0x2D << 6) | ((Vm & 0x10) << 2) | (Vm & 0xF));
|
||||
}
|
||||
}
|
||||
|
||||
void ARMXEmitter::VMOV(ARMReg Dest, ARMReg Src, bool high)
|
||||
{
|
||||
_assert_msg_(DYNA_REC, Src < S0, "This VMOV doesn't support SRC other than ARM Reg");
|
||||
|
||||
@ -136,7 +136,7 @@ protected:
|
||||
u32 Value;
|
||||
|
||||
private:
|
||||
OpType Type;
|
||||
OpType Type;
|
||||
|
||||
// IMM types
|
||||
u8 Rotation; // Only for u8 values
|
||||
@ -154,7 +154,7 @@ public:
|
||||
{
|
||||
Type = type;
|
||||
Value = imm;
|
||||
Rotation = 0;
|
||||
Rotation = 0;
|
||||
}
|
||||
|
||||
Operand2(ARMReg Reg)
|
||||
@ -215,7 +215,7 @@ public:
|
||||
Value = base;
|
||||
Type = TYPE_IMMSREG;
|
||||
}
|
||||
const u32 GetData()
|
||||
u32 GetData()
|
||||
{
|
||||
switch(Type)
|
||||
{
|
||||
@ -232,45 +232,45 @@ public:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
const u32 IMMSR() // IMM shifted register
|
||||
u32 IMMSR() // IMM shifted register
|
||||
{
|
||||
_assert_msg_(DYNA_REC, Type == TYPE_IMMSREG, "IMMSR must be imm shifted register");
|
||||
return ((IndexOrShift & 0x1f) << 7 | (Shift << 5) | Value);
|
||||
}
|
||||
const u32 RSR() // Register shifted register
|
||||
u32 RSR() // Register shifted register
|
||||
{
|
||||
_assert_msg_(DYNA_REC, Type == TYPE_RSR, "RSR must be RSR Of Course");
|
||||
return (IndexOrShift << 8) | (Shift << 5) | 0x10 | Value;
|
||||
}
|
||||
const u32 Rm()
|
||||
u32 Rm()
|
||||
{
|
||||
_assert_msg_(DYNA_REC, Type == TYPE_REG, "Rm must be with Reg");
|
||||
return Value;
|
||||
}
|
||||
|
||||
const u32 Imm5()
|
||||
u32 Imm5()
|
||||
{
|
||||
_assert_msg_(DYNA_REC, (Type == TYPE_IMM), "Imm5 not IMM value");
|
||||
return ((Value & 0x0000001F) << 7);
|
||||
}
|
||||
const u32 Imm8()
|
||||
u32 Imm8()
|
||||
{
|
||||
_assert_msg_(DYNA_REC, (Type == TYPE_IMM), "Imm8Rot not IMM value");
|
||||
return Value & 0xFF;
|
||||
}
|
||||
const u32 Imm8Rot() // IMM8 with Rotation
|
||||
u32 Imm8Rot() // IMM8 with Rotation
|
||||
{
|
||||
_assert_msg_(DYNA_REC, (Type == TYPE_IMM), "Imm8Rot not IMM value");
|
||||
_assert_msg_(DYNA_REC, (Rotation & 0xE1) != 0, "Invalid Operand2: immediate rotation %u", Rotation);
|
||||
return (1 << 25) | (Rotation << 7) | (Value & 0x000000FF);
|
||||
}
|
||||
const u32 Imm12()
|
||||
u32 Imm12()
|
||||
{
|
||||
_assert_msg_(DYNA_REC, (Type == TYPE_IMM), "Imm12 not IMM");
|
||||
return (Value & 0x00000FFF);
|
||||
}
|
||||
|
||||
const u32 Imm12Mod()
|
||||
u32 Imm12Mod()
|
||||
{
|
||||
// This is a IMM12 with the top four bits being rotation and the
|
||||
// bottom eight being a IMM. This is for instructions that need to
|
||||
@ -280,32 +280,32 @@ public:
|
||||
_assert_msg_(DYNA_REC, (Type == TYPE_IMM), "Imm12Mod not IMM");
|
||||
return ((Rotation & 0xF) << 8) | (Value & 0xFF);
|
||||
}
|
||||
const u32 Imm16()
|
||||
u32 Imm16()
|
||||
{
|
||||
_assert_msg_(DYNA_REC, (Type == TYPE_IMM), "Imm16 not IMM");
|
||||
return ( (Value & 0xF000) << 4) | (Value & 0x0FFF);
|
||||
}
|
||||
const u32 Imm16Low()
|
||||
u32 Imm16Low()
|
||||
{
|
||||
return Imm16();
|
||||
}
|
||||
const u32 Imm16High() // Returns high 16bits
|
||||
u32 Imm16High() // Returns high 16bits
|
||||
{
|
||||
_assert_msg_(DYNA_REC, (Type == TYPE_IMM), "Imm16 not IMM");
|
||||
return ( ((Value >> 16) & 0xF000) << 4) | ((Value >> 16) & 0x0FFF);
|
||||
}
|
||||
const u32 Imm24()
|
||||
u32 Imm24()
|
||||
{
|
||||
_assert_msg_(DYNA_REC, (Type == TYPE_IMM), "Imm16 not IMM");
|
||||
return (Value & 0x0FFFFFFF);
|
||||
return (Value & 0x0FFFFFFF);
|
||||
}
|
||||
// NEON and ASIMD specific
|
||||
const u32 Imm8ASIMD()
|
||||
u32 Imm8ASIMD()
|
||||
{
|
||||
_assert_msg_(DYNA_REC, (Type == TYPE_IMM), "Imm8ASIMD not IMM");
|
||||
return ((Value & 0x80) << 17) | ((Value & 0x70) << 12) | (Value & 0xF);
|
||||
}
|
||||
const u32 Imm8VFP()
|
||||
u32 Imm8VFP()
|
||||
{
|
||||
_assert_msg_(DYNA_REC, (Type == TYPE_IMM), "Imm8VFP not IMM");
|
||||
return ((Value & 0xF0) << 12) | (Value & 0xF);
|
||||
@ -339,9 +339,9 @@ struct FixupBranch
|
||||
|
||||
struct LiteralPool
|
||||
{
|
||||
s32 loc;
|
||||
u8* ldr_address;
|
||||
u32 val;
|
||||
s32 loc;
|
||||
u8* ldr_address;
|
||||
u32 val;
|
||||
};
|
||||
|
||||
typedef const u8* JumpTarget;
|
||||
@ -361,6 +361,10 @@ private:
|
||||
void WriteShiftedDataOp(u32 op, bool SetFlags, ARMReg dest, ARMReg src, Operand2 op2);
|
||||
void WriteSignedMultiply(u32 Op, u32 Op2, u32 Op3, ARMReg dest, ARMReg r1, ARMReg r2);
|
||||
|
||||
u32 EncodeVd(ARMReg Vd);
|
||||
u32 EncodeVn(ARMReg Vn);
|
||||
u32 EncodeVm(ARMReg Vm);
|
||||
void WriteVFPDataOp(u32 Op, ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
||||
|
||||
void Write4OpMultiply(u32 op, ARMReg destLo, ARMReg destHi, ARMReg rn, ARMReg rm);
|
||||
|
||||
@ -407,10 +411,10 @@ public:
|
||||
|
||||
// Hint instruction
|
||||
void YIELD();
|
||||
|
||||
|
||||
// Do nothing
|
||||
void NOP(int count = 1); //nop padding - TODO: fast nop slides, for amd and intel (check their manuals)
|
||||
|
||||
|
||||
#ifdef CALL
|
||||
#undef CALL
|
||||
#endif
|
||||
@ -422,7 +426,7 @@ public:
|
||||
FixupBranch BL();
|
||||
FixupBranch BL_CC(CCFlags Cond);
|
||||
void SetJumpTarget(FixupBranch const &branch);
|
||||
|
||||
|
||||
void B (const void *fnptr);
|
||||
void B (ARMReg src);
|
||||
void BL(const void *fnptr);
|
||||
@ -468,7 +472,7 @@ public:
|
||||
void BICS(ARMReg dest, ARMReg src, Operand2 op2);
|
||||
void MVN (ARMReg dest, Operand2 op2);
|
||||
void MVNS(ARMReg dest, Operand2 op2);
|
||||
void MOVW(ARMReg dest, Operand2 op2);
|
||||
void MOVW(ARMReg dest, Operand2 op2);
|
||||
void MOVT(ARMReg dest, Operand2 op2, bool TopBits = false);
|
||||
|
||||
// UDIV and SDIV are only available on CPUs that have
|
||||
@ -510,7 +514,7 @@ public:
|
||||
|
||||
void STMFD(ARMReg dest, bool WriteBack, const int Regnum, ...);
|
||||
void LDMFD(ARMReg dest, bool WriteBack, const int Regnum, ...);
|
||||
|
||||
|
||||
// Exclusive Access operations
|
||||
void LDREX(ARMReg dest, ARMReg base);
|
||||
// result contains the result if the instruction managed to store the value
|
||||
@ -528,16 +532,18 @@ public:
|
||||
// NEON Only
|
||||
void VADD(IntegerSize Size, ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
||||
void VSUB(IntegerSize Size, ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
||||
|
||||
|
||||
// VFP Only
|
||||
void VLDR(ARMReg Dest, ARMReg Base, u16 offset);
|
||||
void VSTR(ARMReg Src, ARMReg Base, u16 offset);
|
||||
void VCMP(ARMReg Vd, ARMReg Vm, bool E);
|
||||
void VLDR(ARMReg Dest, ARMReg Base, s16 offset);
|
||||
void VSTR(ARMReg Src, ARMReg Base, s16 offset);
|
||||
void VCMP(ARMReg Vd, ARMReg Vm);
|
||||
void VCMPE(ARMReg Vd, ARMReg Vm);
|
||||
// Compares against zero
|
||||
void VCMP(ARMReg Vd, bool E);
|
||||
void VCMP(ARMReg Vd);
|
||||
void VCMPE(ARMReg Vd);
|
||||
void VDIV(ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
||||
void VSQRT(ARMReg Vd, ARMReg Vm);
|
||||
|
||||
|
||||
// NEON and VFP
|
||||
void VADD(ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
||||
void VSUB(ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
||||
@ -545,6 +551,7 @@ public:
|
||||
void VNEG(ARMReg Vd, ARMReg Vm);
|
||||
void VMUL(ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
||||
void VMLA(ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
||||
void VMLS(ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
||||
void VMOV(ARMReg Dest, ARMReg Src, bool high);
|
||||
void VMOV(ARMReg Dest, ARMReg Src);
|
||||
void VCVT(ARMReg Dest, ARMReg Src, int flags);
|
||||
@ -608,7 +615,7 @@ public:
|
||||
region_size = 0;
|
||||
}
|
||||
|
||||
bool IsInCodeSpace(u8 *ptr)
|
||||
bool IsInSpace(u8 *ptr)
|
||||
{
|
||||
return ptr >= region && ptr < region + region_size;
|
||||
}
|
||||
|
||||
@ -735,7 +735,7 @@ public:
|
||||
region_size = 0;
|
||||
}
|
||||
|
||||
bool IsInCodeSpace(u8 *ptr)
|
||||
bool IsInSpace(u8 *ptr)
|
||||
{
|
||||
return ptr >= region && ptr < region + region_size;
|
||||
}
|
||||
|
||||
@ -139,7 +139,7 @@ void Jit::Comp_FPUComp(u32 op) {
|
||||
int fs = _FS;
|
||||
int ft = _FT;
|
||||
fpr.MapInIn(fs, ft);
|
||||
VCMP(fpr.R(fs), fpr.R(ft), false);
|
||||
VCMP(fpr.R(fs), fpr.R(ft));
|
||||
VMRS_APSR(); // Move FP flags from FPSCR to APSR (regular flags).
|
||||
switch(opc)
|
||||
{
|
||||
|
||||
Loading…
Reference in New Issue
Block a user