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Port over much of unknown's vfpu jit work to arm. Untested.

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This commit is contained in:
Henrik Rydgard 2013-02-20 00:03:47 +01:00
parent 86fa4b38c3
commit 5a09885a59
10 changed files with 576 additions and 62 deletions
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10
Common/ArmEmitter.cpp
View File

@ -903,6 +903,16 @@ void ARMXEmitter::VMUL(ARMReg Vd, ARMReg Vn, ARMReg Vm)
}
}
void ARMXEmitter::VABS(ARMReg Vd, ARMReg Vn)
{
_assert_msg_(DYNA_REC, 0, "VABS not implemented");
}
void ARMXEmitter::VNEG(ARMReg Vd, ARMReg Vn)
{
_assert_msg_(DYNA_REC, 0, "VNEG not implemented");
}
void ARMXEmitter::VMOV(ARMReg Dest, ARMReg Src, bool high)
{
_assert_msg_(DYNA_REC, Src < S0, "This VMOV doesn't support SRC other than ARM Reg");

2
Common/ArmEmitter.h
View File

@ -510,6 +510,8 @@ public:
// NEON and VFP
void VADD(ARMReg Vd, ARMReg Vn, ARMReg Vm);
void VSUB(ARMReg Vd, ARMReg Vn, ARMReg Vm);
void VABS(ARMReg Vd, ARMReg Vn);
void VNEG(ARMReg Vd, ARMReg Vn);
void VMUL(ARMReg Vd, ARMReg Vn, ARMReg Vm);
void VMOV(ARMReg Dest, ARMReg Src, bool high);
void VMOV(ARMReg Dest, ARMReg Src);

247
Core/MIPS/ARM/ArmCompVFPU.cpp
View File

@ -16,10 +16,35 @@
// #define CONDITIONAL_DISABLE Comp_Generic(op); return;
#define CONDITIONAL_DISABLE ;
#define DISABLE Comp_Generic(op); return;
#define DISABLE {fpr.ReleaseSpillLocks(); Comp_Generic(op); return;}
namespace MIPSComp
{
// Vector regs can overlap in all sorts of swizzled ways.
// This does allow a single overlap in sregs[i].
bool IsOverlapSafeAllowS(int dreg, int di, int sn, u8 sregs[], int tn = 0, u8 tregs[] = NULL)
{
for (int i = 0; i < sn; ++i)
{
if (sregs[i] == dreg && i != di)
return false;
}
for (int i = 0; i < tn; ++i)
{
if (tregs[i] == dreg)
return false;
}
// Hurray, no overlap, we can write directly.
return true;
}
bool IsOverlapSafe(int dreg, int di, int sn, u8 sregs[], int tn = 0, u8 tregs[] = NULL)
{
return IsOverlapSafeAllowS(dreg, di, sn, sregs, tn, tregs) && sregs[di] != dreg;
}
void Jit::Comp_VPFX(u32 op)
{
CONDITIONAL_DISABLE;
@ -42,6 +67,103 @@ namespace MIPSComp
}
}
void Jit::ApplyPrefixST(u8 *vregs, u32 prefix, VectorSize sz) {
if (prefix == 0xE4) return;
int n = GetNumVectorElements(sz);
u8 origV[4];
static const float constantArray[8] = {0.f, 1.f, 2.f, 0.5f, 3.f, 1.f/3.f, 0.25f, 1.f/6.f};
for (int i = 0; i < n; i++)
origV[i] = vregs[i];
for (int i = 0; i < n; i++)
{
int regnum = (prefix >> (i*2)) & 3;
int abs = (prefix >> (8+i)) & 1;
int negate = (prefix >> (16+i)) & 1;
int constants = (prefix >> (12+i)) & 1;
// Unchanged, hurray.
if (!constants && regnum == i && !abs && !negate)
continue;
// This puts the value into a temp reg, so we won't write the modified value back.
vregs[i] = fpr.GetTempV();
fpr.MapRegV(vregs[i], MAP_NOINIT | MAP_DIRTY);
if (!constants) {
// Prefix may say "z, z, z, z" but if this is a pair, we force to x.
// TODO: But some ops seem to use const 0 instead?
if (regnum >= n) {
ERROR_LOG(CPU, "Invalid VFPU swizzle: %08x / %d", prefix, sz);
regnum = 0;
}
if (abs) {
VABS(fpr.V(vregs[i]), fpr.V(origV[regnum]));
} else {
VMOV(fpr.V(vregs[i]), fpr.V(origV[regnum]));
}
} else {
MOVI2R(R0, (u32)(constantArray[regnum + (abs<<2)]));
VMOV(fpr.V(vregs[i]), R0);
}
// TODO: This can be integrated into the VABS / VMOV above, and also the constants.
if (negate)
VNEG(fpr.V(vregs[i]), fpr.V(vregs[i]));
// TODO: This probably means it will swap out soon, inefficiently...
fpr.ReleaseSpillLockV(vregs[i]);
}
}
void Jit::GetVectorRegsPrefixD(u8 *regs, VectorSize sz, int vectorReg) {
_assert_(js.prefixDFlag & JitState::PREFIX_KNOWN);
GetVectorRegs(regs, sz, vectorReg);
if (js.prefixD == 0)
return;
int n = GetNumVectorElements(sz);
for (int i = 0; i < n; i++)
{
// Hopefully this is rare, we'll just write it into a reg we drop.
if (js.VfpuWriteMask(i))
regs[i] = fpr.GetTempV();
}
}
void Jit::ApplyPrefixD(const u8 *vregs, VectorSize sz) {
_assert_(js.prefixDFlag & JitState::PREFIX_KNOWN);
if (!js.prefixD) return;
int n = GetNumVectorElements(sz);
for (int i = 0; i < n; i++)
{
if (js.VfpuWriteMask(i))
continue;
int sat = (js.prefixD >> (i * 2)) & 3;
if (sat == 1)
{
fpr.MapRegV(vregs[i], MAP_DIRTY);
// ARGH this is a pain - no MIN/MAX in non-NEON VFP!
// TODO
//MAXSS(fpr.VX(vregs[i]), M((void *)&zero));
//MINSS(fpr.VX(vregs[i]), M((void *)&one));
}
else if (sat == 3)
{
fpr.MapRegV(vregs[i], MAP_DIRTY);
//MAXSS(fpr.VX(vregs[i]), M((void *)&minus_one));
//MINSS(fpr.VX(vregs[i]), M((void *)&one));
}
}
}
void Jit::Comp_SV(u32 op) {
CONDITIONAL_DISABLE;
@ -125,6 +247,11 @@ namespace MIPSComp
}
}
void Jit::Comp_VVectorInit(u32 op)
{
DISABLE;
}
void Jit::Comp_VDot(u32 op)
{
// DISABLE;
@ -229,9 +356,6 @@ namespace MIPSComp
int n = GetNumVectorElements(sz);
fpr.MapRegsV(sregs, sz, 0);
fpr.MapRegsV(tregs, sz, 0);
fpr.MapReg(TEMP1);
fpr.MapReg(TEMP2);
fpr.MapReg(TEMP3);
for (int i = 0; i < n; ++i) {
fpr.MapReg(TEMP0 + i);
@ -249,6 +373,117 @@ namespace MIPSComp
js.EatPrefix();
}
void Jit::Comp_VV2Op(u32 op) {
CONDITIONAL_DISABLE;
DISABLE;
if (js.HasUnknownPrefix())
DISABLE;
VectorSize sz = GetVecSize(op);
int n = GetNumVectorElements(sz);
u8 sregs[4], dregs[4];
GetVectorRegsPrefixS(sregs, sz, _VS);
GetVectorRegsPrefixD(dregs, sz, _VD);
ARMReg tempxregs[4];
for (int i = 0; i < n; ++i)
{
if (!IsOverlapSafeAllowS(dregs[i], i, n, sregs))
{
int reg = fpr.GetTempV();
fpr.MapRegV(reg, MAP_NOINIT | MAP_DIRTY);
fpr.SpillLockV(reg);
tempxregs[i] = fpr.V(reg);
}
else
{
fpr.MapRegV(dregs[i], (dregs[i] == sregs[i] ? 0 : MAP_NOINIT) | MAP_DIRTY);
fpr.SpillLockV(dregs[i]);
tempxregs[i] = fpr.V(dregs[i]);
}
}
// Warning: sregs[i] and tempxregs[i] may be the same reg.
// Helps for vmov, hurts for vrcp, etc.
for (int i = 0; i < n; ++i)
{
switch ((op >> 16) & 0x1f)
{
case 0: // d[i] = s[i]; break; //vmov
// Probably for swizzle.
VMOV(tempxregs[i], fpr.V(sregs[i]));
break;
case 1: // d[i] = fabsf(s[i]); break; //vabs
//if (!fpr.V(sregs[i]).IsSimpleReg(tempxregs[i]))
VABS(tempxregs[i], fpr.V(sregs[i]));
break;
case 2: // d[i] = -s[i]; break; //vneg
VNEG(tempxregs[i], fpr.V(sregs[i]));
break;
case 4: // if (s[i] < 0) d[i] = 0; else {if(s[i] > 1.0f) d[i] = 1.0f; else d[i] = s[i];} break; // vsat0
DISABLE;
break;
case 5: // if (s[i] < -1.0f) d[i] = -1.0f; else {if(s[i] > 1.0f) d[i] = 1.0f; else d[i] = s[i];} break; // vsat1
DISABLE;
break;
case 16: // d[i] = 1.0f / s[i]; break; //vrcp
MOVI2R(R0, 0x3F800000); // 1.0f
VMOV(S0, R0);
VDIV(tempxregs[i], S0, fpr.V(sregs[i]));
break;
case 17: // d[i] = 1.0f / sqrtf(s[i]); break; //vrsq
MOVI2R(R0, 0x3F800000); // 1.0f
VMOV(S0, R0);
VSQRT(S1, fpr.V(sregs[i]));
VDIV(tempxregs[i], S0, S1);
break;
case 18: // d[i] = sinf((float)M_PI_2 * s[i]); break; //vsin
DISABLE;
break;
case 19: // d[i] = cosf((float)M_PI_2 * s[i]); break; //vcos
DISABLE;
break;
case 20: // d[i] = powf(2.0f, s[i]); break; //vexp2
DISABLE;
break;
case 21: // d[i] = logf(s[i])/log(2.0f); break; //vlog2
DISABLE;
break;
case 22: // d[i] = sqrtf(s[i]); break; //vsqrt
VSQRT(tempxregs[i], fpr.V(sregs[i]));
VABS(tempxregs[i], tempxregs[i]);
break;
case 23: // d[i] = asinf(s[i] * (float)M_2_PI); break; //vasin
DISABLE;
break;
case 24: // d[i] = -1.0f / s[i]; break; // vnrcp
MOVI2R(R0, 0x80000000 | 0x3F800000); // -1.0f
VMOV(S0, R0);
VDIV(tempxregs[i], S0, fpr.V(sregs[i]));
break;
case 26: // d[i] = -sinf((float)M_PI_2 * s[i]); break; // vnsin
DISABLE;
break;
case 28: // d[i] = 1.0f / expf(s[i] * (float)M_LOG2E); break; // vrexp2
DISABLE;
break;
}
}
fpr.MapRegsV(dregs, sz, MAP_NOINIT | MAP_DIRTY);
for (int i = 0; i < n; ++i)
{
VMOV(fpr.V(dregs[i]), tempxregs[i]);
}
ApplyPrefixD(dregs, sz);
fpr.ReleaseSpillLocks();
}
void Jit::Comp_Mftv(u32 op)
{
// DISABLE;
@ -328,4 +563,8 @@ namespace MIPSComp
}
}
void Jit::Comp_Vmmov(u32 op) {
DISABLE;
}
}

17
Core/MIPS/ARM/ArmJit.cpp
View File

@ -62,11 +62,15 @@ Jit::Jit(MIPSState *mips) : blocks(mips), gpr(mips), fpr(mips), mips_(mips)
fpr.SetEmitter(this);
AllocCodeSpace(1024 * 1024 * 16); // 32MB is the absolute max because that's what an ARM branch instruction can reach, backwards and forwards.
GenerateFixedCode();
js.startDefaultPrefix = true;
}
void Jit::DoState(PointerWrap &p)
{
p.Do(js.startDefaultPrefix);
p.DoMarker("Jit");
FlushPrefixV();
}
void Jit::FlushAll()
@ -148,6 +152,17 @@ void Jit::Compile(u32 em_address)
int block_num = blocks.AllocateBlock(em_address);
ArmJitBlock *b = blocks.GetBlock(block_num);
blocks.FinalizeBlock(block_num, jo.enableBlocklink, DoJit(em_address, b));
// Drat. The VFPU hit an uneaten prefix at the end of a block.
if (js.startDefaultPrefix && js.MayHavePrefix())
{
js.startDefaultPrefix = false;
// Our assumptions are all wrong so it's clean-slate time.
ClearCache();
// Let's try that one more time. We won't get back here because we toggled the value.
Compile(em_address);
}
}
void Jit::RunLoopUntil(u64 globalticks)
@ -200,7 +215,7 @@ const u8 *Jit::DoJit(u32 em_address, ArmJitBlock *b)
js.downcountAmount += MIPSGetInstructionCycleEstimate(inst);
MIPSCompileOp(inst);
// FlushAll(); ///HACKK
js.compilerPC += 4;
numInstructions++;
}

51
Core/MIPS/ARM/ArmJit.h
View File

@ -56,29 +56,42 @@ struct ArmJitState
ArmJitBlock *curBlock;
// VFPU prefix magic
bool startDefaultPrefix;
u32 prefixS;
u32 prefixT;
u32 prefixD;
bool writeMask[4];
PrefixState prefixSFlag;
PrefixState prefixTFlag;
PrefixState prefixDFlag;
void PrefixStart() {
if (startDefaultPrefix) {
EatPrefix();
} else {
PrefixUnknown();
}
}
void PrefixUnknown() {
prefixSFlag = PREFIX_UNKNOWN;
prefixTFlag = PREFIX_UNKNOWN;
prefixDFlag = PREFIX_UNKNOWN;
}
bool MayHavePrefix() const {
if (!(prefixSFlag & PREFIX_KNOWN) || !(prefixTFlag & PREFIX_KNOWN) || !(prefixDFlag & PREFIX_KNOWN)) {
if (HasUnknownPrefix()) {
return true;
} else if (prefixS != 0xE4 || prefixT != 0xE4 || prefixD != 0) {
return true;
} else if (writeMask[0] || writeMask[1] || writeMask[2] || writeMask[3]) {
} else if (VfpuWriteMask() != 0) {
return true;
}
return false;
}
bool HasUnknownPrefix() const {
if (!(prefixSFlag & PREFIX_KNOWN) || !(prefixTFlag & PREFIX_KNOWN) || !(prefixDFlag & PREFIX_KNOWN)) {
return true;
}
return false;
}
void EatPrefix() {
if ((prefixSFlag & PREFIX_KNOWN) == 0 || prefixS != 0xE4) {
prefixSFlag = PREFIX_KNOWN_DIRTY;
@ -88,12 +101,19 @@ struct ArmJitState
prefixTFlag = PREFIX_KNOWN_DIRTY;
prefixT = 0xE4;
}
if ((prefixDFlag & PREFIX_KNOWN) == 0 || prefixD != 0x0 || writeMask[0] || writeMask[1] || writeMask[2] || writeMask[3]) {
if ((prefixDFlag & PREFIX_KNOWN) == 0 || prefixD != 0x0 || VfpuWriteMask() != 0) {
prefixDFlag = PREFIX_KNOWN_DIRTY;
prefixD = 0x0;
writeMask[0] = writeMask[1] = writeMask[2] = writeMask[3] = false;
}
}
u8 VfpuWriteMask() const {
_assert_(prefixDFlag & JitState::PREFIX_KNOWN);
return (prefixD >> 8) & 0xF;
}
bool VfpuWriteMask(int i) const {
_assert_(prefixDFlag & JitState::PREFIX_KNOWN);
return (prefixD >> (8 + i)) & 1;
}
};
@ -159,10 +179,14 @@ public:
void Comp_SV(u32 op);
void Comp_SVQ(u32 op);
void Comp_VPFX(u32 op);
void Comp_VVectorInit(u32 op);
void Comp_VDot(u32 op);
void Comp_VecDo3(u32 op);
void Comp_VV2Op(u32 op);
void Comp_Mftv(u32 op);
void Comp_Vmtvc(u32 op);
void Comp_Vmmov(u32 op);
ArmJitBlockCache *GetBlockCache() { return &blocks; }
@ -196,12 +220,27 @@ private:
void CompShiftImm(u32 op, ArmGen::ShiftType shiftType);
void LogBlockNumber();
void ApplyPrefixST(u8 *vregs, u32 prefix, VectorSize sz);
void ApplyPrefixD(const u8 *vregs, VectorSize sz);
void GetVectorRegsPrefixS(u8 *regs, VectorSize sz, int vectorReg) {
_assert_(js.prefixSFlag & JitState::PREFIX_KNOWN);
GetVectorRegs(regs, sz, vectorReg);
ApplyPrefixST(regs, js.prefixS, sz);
}
void GetVectorRegsPrefixT(u8 *regs, VectorSize sz, int vectorReg) {
_assert_(js.prefixTFlag & JitState::PREFIX_KNOWN);
GetVectorRegs(regs, sz, vectorReg);
ApplyPrefixST(regs, js.prefixT, sz);
}
void GetVectorRegsPrefixD(u8 *regs, VectorSize sz, int vectorReg);
/*
void CompImmLogic(u32 op, void (ARMXEmitter::*arith)(int, const OpArg &, const OpArg &));
void CompTriArith(u32 op, void (ARMXEmitter::*arith)(int, const OpArg &, const OpArg &));
void CompShiftImm(u32 op, void (ARMXEmitter::*shift)(int, OpArg, OpArg));
void CompShiftVar(u32 op, void (XEmitter::*shift)(int, OpArg, OpArg));
*/
// Utils

2
Core/MIPS/ARM/ArmRegCache.h
View File

@ -55,7 +55,7 @@ struct RegMIPS {
RegMIPSLoc loc;
// Data (only one of these is used, depending on loc. Could make a union).
u32 imm;
int reg; // reg index (need to add S0 to get ARMReg)
ARMReg reg; // reg index
bool spillLock; // if true, this register cannot be spilled.
// If loc == ML_MEM, it's back in its location in the CPU context struct.
};

32
Core/MIPS/ARM/ArmRegCacheFPU.cpp
View File

@ -38,6 +38,7 @@ void ArmRegCacheFPU::Start(MIPSAnalyst::AnalysisResults &stats) {
mr[i].loc = ML_MEM;
mr[i].reg = INVALID_REG;
mr[i].spillLock = false;
mr[i].tempLock = false;
}
}
@ -109,7 +110,7 @@ allocate:
int bestToSpill = -1;
for (int i = 0; i < allocCount; i++) {
int reg = allocOrder[i] - S0;
if (ar[reg].mipsReg != -1 && mr[ar[reg].mipsReg].spillLock)
if (ar[reg].mipsReg != -1 && (mr[ar[reg].mipsReg].spillLock || mr[ar[reg].mipsReg].tempLock))
continue;
bestToSpill = reg;
break;
@ -242,7 +243,7 @@ void ArmRegCacheFPU::DiscardR(MIPSReg r) {
// IMM is not allowed for FP (yet).
ERROR_LOG(HLE, "Imm in FP register?");
break;
case ML_ARMREG:
if (mr[r].reg == (int)INVALID_REG) {
ERROR_LOG(HLE, "DiscardR: MipsReg had bad ArmReg");
@ -262,8 +263,28 @@ void ArmRegCacheFPU::DiscardR(MIPSReg r) {
}
mr[r].loc = ML_MEM;
mr[r].reg = (int)INVALID_REG;
mr[r].tempLock = false;
// spill lock?
}
bool ArmRegCacheFPU::IsTempX(ARMReg r) const {
return ar[r - S0].mipsReg >= TEMP0;
}
int ArmRegCacheFPU::GetTempR() {
for (int r = TEMP0; r < TEMP0 + NUM_TEMPS; ++r) {
if (mr[r].loc == ML_MEM && !mr[r].tempLock) {
mr[r].tempLock = true;
return r;
}
}
_assert_msg_(DYNA_REC, 0, "Regcache ran out of temp regs, might need to DiscardR() some.");
return -1;
}
void ArmRegCacheFPU::FlushAll() {
// Discard temps!
for (int i = TEMP0; i < TEMP0 + NUM_TEMPS; i++) {
@ -271,7 +292,7 @@ void ArmRegCacheFPU::FlushAll() {
}
for (int i = 0; i < NUM_MIPSFPUREG; i++) {
FlushR(i);
}
}
// Sanity check
for (int i = 0; i < NUM_ARMFPUREG; i++) {
if (ar[i].mipsReg != -1) {
@ -297,9 +318,10 @@ void ArmRegCacheFPU::SpillLock(MIPSReg r1, MIPSReg r2, MIPSReg r3, MIPSReg r4) {
// This is actually pretty slow with all the 160 regs...
void ArmRegCacheFPU::ReleaseSpillLocks() {
for (int i = 0; i < NUM_MIPSFPUREG; i++) {
for (int i = 0; i < NUM_MIPSFPUREG; i++)
mr[i].spillLock = false;
}
for (int i = TEMP0; i < TEMP0 + NUM_TEMPS; ++i)
DiscardR(i);
}
ARMReg ArmRegCacheFPU::R(int mipsReg) {

21
Core/MIPS/ARM/ArmRegCacheFPU.h
View File

@ -28,11 +28,8 @@
using namespace ArmGen;
enum {
NUM_TEMPS = 4,
NUM_TEMPS = 16,
TEMP0 = 32 + 128,
TEMP1 = TEMP0 + 1,
TEMP2 = TEMP0 + 2,
TEMP3 = TEMP0 + 3,
TOTAL_MAPPABLE_MIPSFPUREGS = 32 + 128 + NUM_TEMPS,
};
@ -45,8 +42,9 @@ struct FPURegMIPS {
// Where is this MIPS register?
RegMIPSLoc loc;
// Data (only one of these is used, depending on loc. Could make a union).
ARMReg reg;
int reg;
bool spillLock; // if true, this register cannot be spilled.
bool tempLock;
// If loc == ML_MEM, it's back in its location in the CPU context struct.
};
@ -63,11 +61,16 @@ public:
// Protect the arm register containing a MIPS register from spilling, to ensure that
// it's being kept allocated.
void SpillLock(MIPSReg reg, MIPSReg reg2 = -1, MIPSReg reg3 = -1, MIPSReg reg4 = -1);
void SpillLockV(MIPSReg r) { SpillLock(r + 32); }
void ReleaseSpillLocks();
void ReleaseSpillLock(int mipsreg)
{
mr[mipsreg].spillLock = false;
}
void ReleaseSpillLockV(int mipsreg) {
ReleaseSpillLock(mipsreg + 32);
}
void SetImm(MIPSReg reg, u32 immVal);
bool IsImm(MIPSReg reg) const;
@ -84,7 +87,11 @@ public:
void FlushV(MIPSReg r) { FlushR(r + 32); }
void DiscardR(MIPSReg r);
void DiscardV(MIPSReg r) { DiscardR(r + 32);}
bool IsTempX(ARMReg r) const;
MIPSReg GetTempR();
MIPSReg GetTempV() { return GetTempR() - 32; }
void FlushAll();
ARMReg R(int preg); // Returns a cached register
@ -123,6 +130,6 @@ private:
};
RegARM ar[NUM_ARMFPUREG];
RegMIPS mr[NUM_MIPSFPUREG];
RegMIPS *vr;
FPURegMIPS mr[NUM_MIPSFPUREG];
FPURegMIPS *vr;
};

254
Core/MIPS/x86/CompVFPU.cpp
View File

@ -23,14 +23,14 @@
#include "../MIPSVFPUUtils.h"
#include "RegCache.h"
// VERY UNFINISHED
// VERY UNFINISHED!
// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.
// Currently known non working ones should have DISABLE.
// #define CONDITIONAL_DISABLE { Comp_Generic(op); return; }
// #define CONDITIONAL_DISABLE { fpr.ReleaseSpillLocks(); Comp_Generic(op); return; }
#define CONDITIONAL_DISABLE ;
#define DISABLE { Comp_Generic(op); return; }
#define DISABLE { fpr.ReleaseSpillLocks(); Comp_Generic(op); return; }
#define _RS ((op>>21) & 0x1F)
@ -103,7 +103,7 @@ void Jit::ApplyPrefixST(u8 *vregs, u32 prefix, VectorSize sz) {
if (!constants) {
// Prefix may say "z, z, z, z" but if this is a pair, we force to x.
// TODO: But some ops seem to use const 0 instead?
if (regnum > n) {
if (regnum >= n) {
ERROR_LOG(CPU, "Invalid VFPU swizzle: %08x / %d", prefix, sz);
regnum = 0;
}
@ -167,7 +167,7 @@ void Jit::ApplyPrefixD(const u8 *vregs, VectorSize sz) {
// Vector regs can overlap in all sorts of swizzled ways.
// This does allow a single overlap in sregs[i].
bool IsOverlapSafeAllowS(int dreg, int di, int sn, u8 sregs[], int tn, u8 tregs[])
bool IsOverlapSafeAllowS(int dreg, int di, int sn, u8 sregs[], int tn = 0, u8 tregs[] = NULL)
{
for (int i = 0; i < sn; ++i)
{
@ -184,7 +184,7 @@ bool IsOverlapSafeAllowS(int dreg, int di, int sn, u8 sregs[], int tn, u8 tregs[
return true;
}
bool IsOverlapSafe(int dreg, int di, int sn, u8 sregs[], int tn, u8 tregs[])
bool IsOverlapSafe(int dreg, int di, int sn, u8 sregs[], int tn = 0, u8 tregs[] = NULL)
{
return IsOverlapSafeAllowS(dreg, di, sn, sregs, tn, tregs) && sregs[di] != dreg;
}
@ -336,26 +336,55 @@ void Jit::Comp_SVQ(u32 op)
}
}
void Jit::Comp_VVectorInit(u32 op) {
CONDITIONAL_DISABLE;
if (js.HasUnknownPrefix())
DISABLE;
VectorSize sz = GetVecSize(op);
int n = GetNumVectorElements(sz);
u8 dregs[4];
GetVectorRegsPrefixD(dregs, sz, _VD);
fpr.MapRegsV(dregs, sz, MAP_NOINIT | MAP_DIRTY);
for (int i = 0; i < n; ++i)
{
switch ((op >> 16) & 0xF)
{
case 6: // v=zeros; break; //vzero
MOVSS(fpr.VX(dregs[i]), M((void *) &zero));
break;
case 7: // v=ones; break; //vone
MOVSS(fpr.VX(dregs[i]), M((void *) &one));
break;
default:
DISABLE;
break;
}
}
ApplyPrefixD(dregs, sz);
fpr.ReleaseSpillLocks();
}
void Jit::Comp_VDot(u32 op) {
CONDITIONAL_DISABLE;
if (js.HasUnknownPrefix()) {
Comp_Generic(op);
return;
}
if (js.HasUnknownPrefix())
DISABLE;
int vd = _VD;
int vs = _VS;
int vt = _VT;
VectorSize sz = GetVecSize(op);
int n = GetNumVectorElements(sz);
// TODO: Force read one of them into regs? probably not.
u8 sregs[4], tregs[4], dregs[1];
GetVectorRegsPrefixS(sregs, sz, vs);
GetVectorRegsPrefixT(tregs, sz, vt);
GetVectorRegsPrefixD(dregs, V_Single, vd);
GetVectorRegsPrefixS(sregs, sz, _VS);
GetVectorRegsPrefixT(tregs, sz, _VT);
GetVectorRegsPrefixD(dregs, V_Single, _VD);
int n = GetNumVectorElements(sz);
X64Reg tempxreg = XMM0;
if (IsOverlapSafe(dregs[0], 0, n, sregs, n, tregs))
{
@ -387,20 +416,8 @@ void Jit::Comp_VDot(u32 op) {
void Jit::Comp_VecDo3(u32 op) {
CONDITIONAL_DISABLE;
if (js.HasUnknownPrefix()) {
Comp_Generic(op);
return;
}
int vd = _VD;
int vs = _VS;
int vt = _VT;
VectorSize sz = GetVecSize(op);
u8 sregs[4], tregs[4], dregs[4];
GetVectorRegsPrefixS(sregs, sz, vs);
GetVectorRegsPrefixT(tregs, sz, vt);
GetVectorRegsPrefixD(dregs, sz, vd);
if (js.HasUnknownPrefix())
DISABLE;
void (XEmitter::*xmmop)(X64Reg, OpArg) = NULL;
switch (op >> 26)
@ -430,14 +447,16 @@ void Jit::Comp_VecDo3(u32 op) {
}
if (xmmop == NULL)
{
fpr.ReleaseSpillLocks();
Comp_Generic(op);
return;
}
DISABLE;
VectorSize sz = GetVecSize(op);
int n = GetNumVectorElements(sz);
u8 sregs[4], tregs[4], dregs[4];
GetVectorRegsPrefixS(sregs, sz, _VS);
GetVectorRegsPrefixT(tregs, sz, _VT);
GetVectorRegsPrefixD(dregs, sz, _VD);
X64Reg tempxregs[4];
for (int i = 0; i < n; ++i)
{
@ -480,6 +499,125 @@ void Jit::Comp_VecDo3(u32 op) {
fpr.ReleaseSpillLocks();
}
void Jit::Comp_VV2Op(u32 op) {
CONDITIONAL_DISABLE;
if (js.HasUnknownPrefix())
DISABLE;
VectorSize sz = GetVecSize(op);
int n = GetNumVectorElements(sz);
u8 sregs[4], dregs[4];
GetVectorRegsPrefixS(sregs, sz, _VS);
GetVectorRegsPrefixD(dregs, sz, _VD);
X64Reg tempxregs[4];
for (int i = 0; i < n; ++i)
{
if (!IsOverlapSafeAllowS(dregs[i], i, n, sregs))
{
int reg = fpr.GetTempV();
fpr.MapRegV(reg, MAP_NOINIT | MAP_DIRTY);
fpr.SpillLockV(reg);
tempxregs[i] = fpr.VX(reg);
}
else
{
fpr.MapRegV(dregs[i], (dregs[i] == sregs[i] ? 0 : MAP_NOINIT) | MAP_DIRTY);
fpr.SpillLockV(dregs[i]);
tempxregs[i] = fpr.VX(dregs[i]);
}
}
// Warning: sregs[i] and tempxregs[i] may be the same reg.
// Helps for vmov, hurts for vrcp, etc.
for (int i = 0; i < n; ++i)
{
switch ((op >> 16) & 0x1f)
{
case 0: // d[i] = s[i]; break; //vmov
// Probably for swizzle.
if (!fpr.V(sregs[i]).IsSimpleReg(tempxregs[i]))
MOVSS(tempxregs[i], fpr.V(sregs[i]));
break;
case 1: // d[i] = fabsf(s[i]); break; //vabs
if (!fpr.V(sregs[i]).IsSimpleReg(tempxregs[i]))
MOVSS(tempxregs[i], fpr.V(sregs[i]));
ANDPS(tempxregs[i], M((void *)&noSignMask));
break;
case 2: // d[i] = -s[i]; break; //vneg
if (!fpr.V(sregs[i]).IsSimpleReg(tempxregs[i]))
MOVSS(tempxregs[i], fpr.V(sregs[i]));
XORPS(tempxregs[i], M((void *)&signBitLower));
break;
case 4: // if (s[i] < 0) d[i] = 0; else {if(s[i] > 1.0f) d[i] = 1.0f; else d[i] = s[i];} break; // vsat0
if (!fpr.V(sregs[i]).IsSimpleReg(tempxregs[i]))
MOVSS(tempxregs[i], fpr.V(sregs[i]));
// TODO: Doesn't handle NaN correctly.
MAXSS(tempxregs[i], M((void *)&zero));
MINSS(tempxregs[i], M((void *)&one));
break;
case 5: // if (s[i] < -1.0f) d[i] = -1.0f; else {if(s[i] > 1.0f) d[i] = 1.0f; else d[i] = s[i];} break; // vsat1
if (!fpr.V(sregs[i]).IsSimpleReg(tempxregs[i]))
MOVSS(tempxregs[i], fpr.V(sregs[i]));
// TODO: Doesn't handle NaN correctly.
MAXSS(tempxregs[i], M((void *)&minus_one));
MINSS(tempxregs[i], M((void *)&one));
break;
case 16: // d[i] = 1.0f / s[i]; break; //vrcp
MOVSS(XMM0, M((void *)&one));
DIVSS(XMM0, fpr.V(sregs[i]));
MOVSS(tempxregs[i], R(XMM0));
break;
case 17: // d[i] = 1.0f / sqrtf(s[i]); break; //vrsq
SQRTSS(XMM0, fpr.V(sregs[i]));
MOVSS(tempxregs[i], M((void *)&one));
DIVSS(tempxregs[i], R(XMM0));
break;
case 18: // d[i] = sinf((float)M_PI_2 * s[i]); break; //vsin
DISABLE;
break;
case 19: // d[i] = cosf((float)M_PI_2 * s[i]); break; //vcos
DISABLE;
break;
case 20: // d[i] = powf(2.0f, s[i]); break; //vexp2
DISABLE;
break;
case 21: // d[i] = logf(s[i])/log(2.0f); break; //vlog2
DISABLE;
break;
case 22: // d[i] = sqrtf(s[i]); break; //vsqrt
SQRTSS(tempxregs[i], fpr.V(sregs[i]));
ANDPS(tempxregs[i], M((void *)&noSignMask));
break;
case 23: // d[i] = asinf(s[i] * (float)M_2_PI); break; //vasin
DISABLE;
break;
case 24: // d[i] = -1.0f / s[i]; break; // vnrcp
MOVSS(XMM0, M((void *)&minus_one));
DIVSS(XMM0, fpr.V(sregs[i]));
MOVSS(tempxregs[i], R(XMM0));
break;
case 26: // d[i] = -sinf((float)M_PI_2 * s[i]); break; // vnsin
DISABLE;
break;
case 28: // d[i] = 1.0f / expf(s[i] * (float)M_LOG2E); break; // vrexp2
DISABLE;
break;
}
}
for (int i = 0; i < n; ++i)
{
if (!fpr.V(dregs[i]).IsSimpleReg(tempxregs[i]))
MOVSS(fpr.V(dregs[i]), tempxregs[i]);
}
ApplyPrefixD(dregs, sz);
fpr.ReleaseSpillLocks();
}
void Jit::Comp_Mftv(u32 op) {
CONDITIONAL_DISABLE;
@ -541,7 +679,7 @@ void Jit::Comp_Vmtvc(u32 op) {
int imm = op & 0xFF;
if (imm >= 128 && imm < 128 + VFPU_CTRL_MAX) {
fpr.MapRegV(vs, 0);
MOVSS(M(&currentMIPS->vfpuCtrl[imm - 128]), fpr.RX(vs));
MOVSS(M(&currentMIPS->vfpuCtrl[imm - 128]), fpr.VX(vs));
fpr.ReleaseSpillLocks();
if (imm - 128 == VFPU_CTRL_SPREFIX) {
@ -554,4 +692,46 @@ void Jit::Comp_Vmtvc(u32 op) {
}
}
void Jit::Comp_Vmmov(u32 op) {
CONDITIONAL_DISABLE;
// TODO: This probably ignores prefixes?
if (js.MayHavePrefix())
DISABLE;
MatrixSize sz = GetMtxSize(op);
int n = GetMatrixSide(sz);
u8 sregs[16], dregs[16];
GetMatrixRegs(sregs, sz, _VS);
GetMatrixRegs(dregs, sz, _VD);
// TODO: gas doesn't allow overlap, what does the PSP do?
// Potentially detect overlap or the safe direction to move in, or just DISABLE?
// This is very not optimal, blows the regcache everytime.
u8 tempregs[16];
for (int a = 0; a < n; a++)
{
for (int b = 0; b < n; b++)
{
u8 temp = (u8) fpr.GetTempV();
fpr.MapRegV(temp, MAP_NOINIT | MAP_DIRTY);
MOVSS(fpr.VX(temp), fpr.V(sregs[a * 4 + b]));
fpr.StoreFromRegisterV(temp);
tempregs[a * 4 + b] = temp;
}
}
for (int a = 0; a < n; a++)
{
for (int b = 0; b < n; b++)
{
u8 temp = tempregs[a * 4 + b];
fpr.MapRegV(temp, 0);
MOVSS(fpr.V(dregs[a * 4 + b]), fpr.VX(temp));
}
}
fpr.ReleaseSpillLocks();
}
}

2
native

@ -1 +1 @@
Subproject commit f5e7bd5a9c3e4b39a4eac71b577f06ad54f2bc96
Subproject commit f807e225f75b131e614c92770fb93a5e902be22b