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[Common/Data/GPU/Input/System/UI] Added const reference for function params

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This commit is contained in:
Herman Semenov 2023-12-14 14:21:11 +03:00
parent 60402909f8
commit 5a0d54be83
14 changed files with 79 additions and 79 deletions
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64
Common/Arm64Emitter.cpp
View File

@ -552,7 +552,7 @@ void ARM64XEmitter::EncodeSystemInst(u32 op0, u32 op1, u32 CRn, u32 CRm, u32 op2
Write32((0x354 << 22) | (op0 << 19) | (op1 << 16) | (CRn << 12) | (CRm << 8) | (op2 << 5) | Rt); Write32((0x354 << 22) | (op0 << 19) | (op1 << 16) | (CRn << 12) | (CRm << 8) | (op2 << 5) | Rt);
} }
void ARM64XEmitter::EncodeArithmeticInst(u32 instenc, bool flags, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Option) void ARM64XEmitter::EncodeArithmeticInst(u32 instenc, bool flags, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, const ArithOption &Option)
{ {
bool b64Bit = Is64Bit(Rd); bool b64Bit = Is64Bit(Rd);
@ -646,7 +646,7 @@ void ARM64XEmitter::EncodeData3SrcInst(u32 instenc, ARM64Reg Rd, ARM64Reg Rn, AR
(Ra << 10) | (Rn << 5) | Rd); (Ra << 10) | (Rn << 5) | Rd);
} }
void ARM64XEmitter::EncodeLogicalInst(u32 instenc, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Shift) void ARM64XEmitter::EncodeLogicalInst(u32 instenc, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, const ArithOption &Shift)
{ {
bool b64Bit = Is64Bit(Rd); bool b64Bit = Is64Bit(Rd);
@ -771,7 +771,7 @@ void ARM64XEmitter::EncodeBitfieldMOVInst(u32 op, ARM64Reg Rd, ARM64Reg Rn, u32
(immr << 16) | (imms << 10) | (Rn << 5) | Rd); (immr << 16) | (imms << 10) | (Rn << 5) | Rd);
} }
void ARM64XEmitter::EncodeLoadStoreRegisterOffset(u32 size, u32 opc, ARM64Reg Rt, ARM64Reg Rn, ArithOption Rm) void ARM64XEmitter::EncodeLoadStoreRegisterOffset(u32 size, u32 opc, ARM64Reg Rt, ARM64Reg Rn, const ArithOption &Rm)
{ {
Rt = DecodeReg(Rt); Rt = DecodeReg(Rt);
Rn = DecodeReg(Rn); Rn = DecodeReg(Rn);
@ -1186,7 +1186,7 @@ void ARM64XEmitter::ADD(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
ADD(Rd, Rn, Rm, ArithOption(Rd, ST_LSL, 0)); ADD(Rd, Rn, Rm, ArithOption(Rd, ST_LSL, 0));
} }
void ARM64XEmitter::ADD(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Option) void ARM64XEmitter::ADD(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, const ArithOption &Option)
{ {
EncodeArithmeticInst(0, false, Rd, Rn, Rm, Option); EncodeArithmeticInst(0, false, Rd, Rn, Rm, Option);
} }
@ -1196,7 +1196,7 @@ void ARM64XEmitter::ADDS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
EncodeArithmeticInst(0, true, Rd, Rn, Rm, ArithOption(Rd, ST_LSL, 0)); EncodeArithmeticInst(0, true, Rd, Rn, Rm, ArithOption(Rd, ST_LSL, 0));
} }
void ARM64XEmitter::ADDS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Option) void ARM64XEmitter::ADDS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, const ArithOption &Option)
{ {
EncodeArithmeticInst(0, true, Rd, Rn, Rm, Option); EncodeArithmeticInst(0, true, Rd, Rn, Rm, Option);
} }
@ -1206,7 +1206,7 @@ void ARM64XEmitter::SUB(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
SUB(Rd, Rn, Rm, ArithOption(Rd, ST_LSL, 0)); SUB(Rd, Rn, Rm, ArithOption(Rd, ST_LSL, 0));
} }
void ARM64XEmitter::SUB(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Option) void ARM64XEmitter::SUB(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, const ArithOption &Option)
{ {
EncodeArithmeticInst(1, false, Rd, Rn, Rm, Option); EncodeArithmeticInst(1, false, Rd, Rn, Rm, Option);
} }
@ -1216,7 +1216,7 @@ void ARM64XEmitter::SUBS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
EncodeArithmeticInst(1, true, Rd, Rn, Rm, ArithOption(Rd, ST_LSL, 0)); EncodeArithmeticInst(1, true, Rd, Rn, Rm, ArithOption(Rd, ST_LSL, 0));
} }
void ARM64XEmitter::SUBS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Option) void ARM64XEmitter::SUBS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, const ArithOption &Option)
{ {
EncodeArithmeticInst(1, true, Rd, Rn, Rm, Option); EncodeArithmeticInst(1, true, Rd, Rn, Rm, Option);
} }
@ -1226,7 +1226,7 @@ void ARM64XEmitter::CMN(ARM64Reg Rn, ARM64Reg Rm)
CMN(Rn, Rm, ArithOption(Rn, ST_LSL, 0)); CMN(Rn, Rm, ArithOption(Rn, ST_LSL, 0));
} }
void ARM64XEmitter::CMN(ARM64Reg Rn, ARM64Reg Rm, ArithOption Option) void ARM64XEmitter::CMN(ARM64Reg Rn, ARM64Reg Rm, const ArithOption &Option)
{ {
EncodeArithmeticInst(0, true, Is64Bit(Rn) ? ZR : WZR, Rn, Rm, Option); EncodeArithmeticInst(0, true, Is64Bit(Rn) ? ZR : WZR, Rn, Rm, Option);
} }
@ -1236,7 +1236,7 @@ void ARM64XEmitter::CMP(ARM64Reg Rn, ARM64Reg Rm)
CMP(Rn, Rm, ArithOption(Rn, ST_LSL, 0)); CMP(Rn, Rm, ArithOption(Rn, ST_LSL, 0));
} }
void ARM64XEmitter::CMP(ARM64Reg Rn, ARM64Reg Rm, ArithOption Option) void ARM64XEmitter::CMP(ARM64Reg Rn, ARM64Reg Rm, const ArithOption &Option)
{ {
EncodeArithmeticInst(1, true, Is64Bit(Rn) ? ZR : WZR, Rn, Rm, Option); EncodeArithmeticInst(1, true, Is64Bit(Rn) ? ZR : WZR, Rn, Rm, Option);
} }
@ -1432,44 +1432,44 @@ void ARM64XEmitter::MNEG(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
} }
// Logical (shifted register) // Logical (shifted register)
void ARM64XEmitter::AND(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Shift) void ARM64XEmitter::AND(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, const ArithOption &Shift)
{ {
EncodeLogicalInst(0, Rd, Rn, Rm, Shift); EncodeLogicalInst(0, Rd, Rn, Rm, Shift);
} }
void ARM64XEmitter::BIC(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Shift) void ARM64XEmitter::BIC(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, const ArithOption &Shift)
{ {
EncodeLogicalInst(1, Rd, Rn, Rm, Shift); EncodeLogicalInst(1, Rd, Rn, Rm, Shift);
} }
void ARM64XEmitter::ORR(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Shift) void ARM64XEmitter::ORR(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, const ArithOption &Shift)
{ {
EncodeLogicalInst(2, Rd, Rn, Rm, Shift); EncodeLogicalInst(2, Rd, Rn, Rm, Shift);
} }
void ARM64XEmitter::ORN(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Shift) void ARM64XEmitter::ORN(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, const ArithOption &Shift)
{ {
EncodeLogicalInst(3, Rd, Rn, Rm, Shift); EncodeLogicalInst(3, Rd, Rn, Rm, Shift);
} }
void ARM64XEmitter::EOR(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Shift) void ARM64XEmitter::EOR(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, const ArithOption &Shift)
{ {
EncodeLogicalInst(4, Rd, Rn, Rm, Shift); EncodeLogicalInst(4, Rd, Rn, Rm, Shift);
} }
void ARM64XEmitter::EON(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Shift) void ARM64XEmitter::EON(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, const ArithOption &Shift)
{ {
EncodeLogicalInst(5, Rd, Rn, Rm, Shift); EncodeLogicalInst(5, Rd, Rn, Rm, Shift);
} }
void ARM64XEmitter::ANDS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Shift) void ARM64XEmitter::ANDS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, const ArithOption &Shift)
{ {
EncodeLogicalInst(6, Rd, Rn, Rm, Shift); EncodeLogicalInst(6, Rd, Rn, Rm, Shift);
} }
void ARM64XEmitter::BICS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Shift) void ARM64XEmitter::BICS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, const ArithOption &Shift)
{ {
EncodeLogicalInst(7, Rd, Rn, Rm, Shift); EncodeLogicalInst(7, Rd, Rn, Rm, Shift);
} }
void ARM64XEmitter::TST(ARM64Reg Rn, ARM64Reg Rm, ArithOption Shift) void ARM64XEmitter::TST(ARM64Reg Rn, ARM64Reg Rm, const ArithOption &Shift)
{ {
ANDS(Is64Bit(Rn) ? ZR : WZR, Rn, Rm, Shift); ANDS(Is64Bit(Rn) ? ZR : WZR, Rn, Rm, Shift);
} }
void ARM64XEmitter::MOV(ARM64Reg Rd, ARM64Reg Rm, ArithOption Shift) { void ARM64XEmitter::MOV(ARM64Reg Rd, ARM64Reg Rm, const ArithOption &Shift) {
ORR(Rd, Is64Bit(Rd) ? ZR : WZR, Rm, Shift); ORR(Rd, Is64Bit(Rd) ? ZR : WZR, Rm, Shift);
} }
@ -1835,47 +1835,47 @@ void ARM64XEmitter::LDRSW(IndexType type, ARM64Reg Rt, ARM64Reg Rn, s32 imm)
} }
// Load/Store register (register offset) // Load/Store register (register offset)
void ARM64XEmitter::STRB(ARM64Reg Rt, ARM64Reg Rn, ArithOption Rm) void ARM64XEmitter::STRB(ARM64Reg Rt, ARM64Reg Rn, const ArithOption &Rm)
{ {
EncodeLoadStoreRegisterOffset(0, 0, Rt, Rn, Rm); EncodeLoadStoreRegisterOffset(0, 0, Rt, Rn, Rm);
} }
void ARM64XEmitter::LDRB(ARM64Reg Rt, ARM64Reg Rn, ArithOption Rm) void ARM64XEmitter::LDRB(ARM64Reg Rt, ARM64Reg Rn, const ArithOption &Rm)
{ {
EncodeLoadStoreRegisterOffset(0, 1, Rt, Rn, Rm); EncodeLoadStoreRegisterOffset(0, 1, Rt, Rn, Rm);
} }
void ARM64XEmitter::LDRSB(ARM64Reg Rt, ARM64Reg Rn, ArithOption Rm) void ARM64XEmitter::LDRSB(ARM64Reg Rt, ARM64Reg Rn, const ArithOption &Rm)
{ {
bool b64Bit = Is64Bit(Rt); bool b64Bit = Is64Bit(Rt);
EncodeLoadStoreRegisterOffset(0, 3 - b64Bit, Rt, Rn, Rm); EncodeLoadStoreRegisterOffset(0, 3 - b64Bit, Rt, Rn, Rm);
} }
void ARM64XEmitter::STRH(ARM64Reg Rt, ARM64Reg Rn, ArithOption Rm) void ARM64XEmitter::STRH(ARM64Reg Rt, ARM64Reg Rn, const ArithOption &Rm)
{ {
EncodeLoadStoreRegisterOffset(1, 0, Rt, Rn, Rm); EncodeLoadStoreRegisterOffset(1, 0, Rt, Rn, Rm);
} }
void ARM64XEmitter::LDRH(ARM64Reg Rt, ARM64Reg Rn, ArithOption Rm) void ARM64XEmitter::LDRH(ARM64Reg Rt, ARM64Reg Rn, const ArithOption &Rm)
{ {
EncodeLoadStoreRegisterOffset(1, 1, Rt, Rn, Rm); EncodeLoadStoreRegisterOffset(1, 1, Rt, Rn, Rm);
} }
void ARM64XEmitter::LDRSH(ARM64Reg Rt, ARM64Reg Rn, ArithOption Rm) void ARM64XEmitter::LDRSH(ARM64Reg Rt, ARM64Reg Rn, const ArithOption &Rm)
{ {
bool b64Bit = Is64Bit(Rt); bool b64Bit = Is64Bit(Rt);
EncodeLoadStoreRegisterOffset(1, 3 - b64Bit, Rt, Rn, Rm); EncodeLoadStoreRegisterOffset(1, 3 - b64Bit, Rt, Rn, Rm);
} }
void ARM64XEmitter::STR(ARM64Reg Rt, ARM64Reg Rn, ArithOption Rm) void ARM64XEmitter::STR(ARM64Reg Rt, ARM64Reg Rn, const ArithOption &Rm)
{ {
bool b64Bit = Is64Bit(Rt); bool b64Bit = Is64Bit(Rt);
EncodeLoadStoreRegisterOffset(2 + b64Bit, 0, Rt, Rn, Rm); EncodeLoadStoreRegisterOffset(2 + b64Bit, 0, Rt, Rn, Rm);
} }
void ARM64XEmitter::LDR(ARM64Reg Rt, ARM64Reg Rn, ArithOption Rm) void ARM64XEmitter::LDR(ARM64Reg Rt, ARM64Reg Rn, const ArithOption &Rm)
{ {
bool b64Bit = Is64Bit(Rt); bool b64Bit = Is64Bit(Rt);
EncodeLoadStoreRegisterOffset(2 + b64Bit, 1, Rt, Rn, Rm); EncodeLoadStoreRegisterOffset(2 + b64Bit, 1, Rt, Rn, Rm);
} }
void ARM64XEmitter::LDRSW(ARM64Reg Rt, ARM64Reg Rn, ArithOption Rm) void ARM64XEmitter::LDRSW(ARM64Reg Rt, ARM64Reg Rn, const ArithOption &Rm)
{ {
EncodeLoadStoreRegisterOffset(2, 2, Rt, Rn, Rm); EncodeLoadStoreRegisterOffset(2, 2, Rt, Rn, Rm);
} }
void ARM64XEmitter::PRFM(ARM64Reg Rt, ARM64Reg Rn, ArithOption Rm) void ARM64XEmitter::PRFM(ARM64Reg Rt, ARM64Reg Rn, const ArithOption &Rm)
{ {
EncodeLoadStoreRegisterOffset(3, 2, Rt, Rn, Rm); EncodeLoadStoreRegisterOffset(3, 2, Rt, Rn, Rm);
} }
@ -2491,7 +2491,7 @@ void ARM64FloatEmitter::EncodeLoadStorePair(u32 size, bool load, IndexType type,
} }
void ARM64FloatEmitter::EncodeLoadStoreRegisterOffset(u32 size, bool load, ARM64Reg Rt, ARM64Reg Rn, ArithOption Rm) void ARM64FloatEmitter::EncodeLoadStoreRegisterOffset(u32 size, bool load, ARM64Reg Rt, ARM64Reg Rn, const ArithOption &Rm)
{ {
_assert_msg_(Rm.GetType() == ArithOption::TYPE_EXTENDEDREG, "%s must contain an extended reg as Rm!", __FUNCTION__); _assert_msg_(Rm.GetType() == ArithOption::TYPE_EXTENDEDREG, "%s must contain an extended reg as Rm!", __FUNCTION__);
@ -2941,11 +2941,11 @@ void ARM64FloatEmitter::STP(u8 size, IndexType type, ARM64Reg Rt, ARM64Reg Rt2,
} }
// Loadstore register offset // Loadstore register offset
void ARM64FloatEmitter::STR(u8 size, ARM64Reg Rt, ARM64Reg Rn, ArithOption Rm) void ARM64FloatEmitter::STR(u8 size, ARM64Reg Rt, ARM64Reg Rn, const ArithOption &Rm)
{ {
EncodeLoadStoreRegisterOffset(size, false, Rt, Rn, Rm); EncodeLoadStoreRegisterOffset(size, false, Rt, Rn, Rm);
} }
void ARM64FloatEmitter::LDR(u8 size, ARM64Reg Rt, ARM64Reg Rn, ArithOption Rm) void ARM64FloatEmitter::LDR(u8 size, ARM64Reg Rt, ARM64Reg Rn, const ArithOption &Rm)
{ {
EncodeLoadStoreRegisterOffset(size, true, Rt, Rn, Rm); EncodeLoadStoreRegisterOffset(size, true, Rt, Rn, Rm);
} }

64
Common/Arm64Emitter.h
View File

@ -370,7 +370,7 @@ private:
void EncodeUnconditionalBranchInst(u32 opc, u32 op2, u32 op3, u32 op4, ARM64Reg Rn); void EncodeUnconditionalBranchInst(u32 opc, u32 op2, u32 op3, u32 op4, ARM64Reg Rn);
void EncodeExceptionInst(u32 instenc, u32 imm); void EncodeExceptionInst(u32 instenc, u32 imm);
void EncodeSystemInst(u32 op0, u32 op1, u32 CRn, u32 CRm, u32 op2, ARM64Reg Rt); void EncodeSystemInst(u32 op0, u32 op1, u32 CRn, u32 CRm, u32 op2, ARM64Reg Rt);
void EncodeArithmeticInst(u32 instenc, bool flags, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Option); void EncodeArithmeticInst(u32 instenc, bool flags, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, const ArithOption &Option);
void EncodeArithmeticCarryInst(u32 op, bool flags, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm); void EncodeArithmeticCarryInst(u32 op, bool flags, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
void EncodeCondCompareImmInst(u32 op, ARM64Reg Rn, u32 imm, u32 nzcv, CCFlags cond); void EncodeCondCompareImmInst(u32 op, ARM64Reg Rn, u32 imm, u32 nzcv, CCFlags cond);
void EncodeCondCompareRegInst(u32 op, ARM64Reg Rn, ARM64Reg Rm, u32 nzcv, CCFlags cond); void EncodeCondCompareRegInst(u32 op, ARM64Reg Rn, ARM64Reg Rm, u32 nzcv, CCFlags cond);
@ -378,7 +378,7 @@ private:
void EncodeData1SrcInst(u32 instenc, ARM64Reg Rd, ARM64Reg Rn); void EncodeData1SrcInst(u32 instenc, ARM64Reg Rd, ARM64Reg Rn);
void EncodeData2SrcInst(u32 instenc, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm); void EncodeData2SrcInst(u32 instenc, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
void EncodeData3SrcInst(u32 instenc, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ARM64Reg Ra); void EncodeData3SrcInst(u32 instenc, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ARM64Reg Ra);
void EncodeLogicalInst(u32 instenc, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Shift); void EncodeLogicalInst(u32 instenc, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, const ArithOption &Shift);
void EncodeLoadRegisterInst(u32 bitop, ARM64Reg Rt, u32 imm); void EncodeLoadRegisterInst(u32 bitop, ARM64Reg Rt, u32 imm);
void EncodeLoadStoreExcInst(u32 instenc, ARM64Reg Rs, ARM64Reg Rt2, ARM64Reg Rn, ARM64Reg Rt); void EncodeLoadStoreExcInst(u32 instenc, ARM64Reg Rs, ARM64Reg Rt2, ARM64Reg Rn, ARM64Reg Rt);
void EncodeLoadStorePairedInst(u32 op, ARM64Reg Rt, ARM64Reg Rt2, ARM64Reg Rn, u32 imm); void EncodeLoadStorePairedInst(u32 op, ARM64Reg Rt, ARM64Reg Rt2, ARM64Reg Rn, u32 imm);
@ -386,7 +386,7 @@ private:
void EncodeLoadStoreIndexedInst(u32 op, ARM64Reg Rt, ARM64Reg Rn, s32 imm, u8 size); void EncodeLoadStoreIndexedInst(u32 op, ARM64Reg Rt, ARM64Reg Rn, s32 imm, u8 size);
void EncodeMOVWideInst(u32 op, ARM64Reg Rd, u32 imm, ShiftAmount pos); void EncodeMOVWideInst(u32 op, ARM64Reg Rd, u32 imm, ShiftAmount pos);
void EncodeBitfieldMOVInst(u32 op, ARM64Reg Rd, ARM64Reg Rn, u32 immr, u32 imms); void EncodeBitfieldMOVInst(u32 op, ARM64Reg Rd, ARM64Reg Rn, u32 immr, u32 imms);
void EncodeLoadStoreRegisterOffset(u32 size, u32 opc, ARM64Reg Rt, ARM64Reg Rn, ArithOption Rm); void EncodeLoadStoreRegisterOffset(u32 size, u32 opc, ARM64Reg Rt, ARM64Reg Rn, const ArithOption &Rm);
void EncodeAddSubImmInst(u32 op, bool flags, u32 shift, u32 imm, ARM64Reg Rn, ARM64Reg Rd); void EncodeAddSubImmInst(u32 op, bool flags, u32 shift, u32 imm, ARM64Reg Rn, ARM64Reg Rd);
void EncodeLogicalImmInst(u32 op, ARM64Reg Rd, ARM64Reg Rn, u32 immr, u32 imms, int n); void EncodeLogicalImmInst(u32 op, ARM64Reg Rd, ARM64Reg Rn, u32 immr, u32 imms, int n);
void EncodeLoadStorePair(u32 op, u32 load, IndexType type, ARM64Reg Rt, ARM64Reg Rt2, ARM64Reg Rn, s32 imm); void EncodeLoadStorePair(u32 op, u32 load, IndexType type, ARM64Reg Rt, ARM64Reg Rt2, ARM64Reg Rn, s32 imm);
@ -479,17 +479,17 @@ public:
// Add/Subtract (Extended/Shifted register) // Add/Subtract (Extended/Shifted register)
void ADD(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm); void ADD(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
void ADD(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Option); void ADD(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, const ArithOption &Option);
void ADDS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm); void ADDS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
void ADDS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Option); void ADDS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, const ArithOption &Option);
void SUB(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm); void SUB(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
void SUB(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Option); void SUB(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, const ArithOption &Option);
void SUBS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm); void SUBS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
void SUBS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Option); void SUBS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, const ArithOption &Option);
void CMN(ARM64Reg Rn, ARM64Reg Rm); void CMN(ARM64Reg Rn, ARM64Reg Rm);
void CMN(ARM64Reg Rn, ARM64Reg Rm, ArithOption Option); void CMN(ARM64Reg Rn, ARM64Reg Rm, const ArithOption &Option);
void CMP(ARM64Reg Rn, ARM64Reg Rm); void CMP(ARM64Reg Rn, ARM64Reg Rm);
void CMP(ARM64Reg Rn, ARM64Reg Rm, ArithOption Option); void CMP(ARM64Reg Rn, ARM64Reg Rm, const ArithOption &Option);
// Add/Subtract (with carry) // Add/Subtract (with carry)
void ADC(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm); void ADC(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
@ -559,15 +559,15 @@ public:
void MNEG(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm); void MNEG(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
// Logical (shifted register) // Logical (shifted register)
void AND(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Shift); void AND(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, const ArithOption &Shift);
void BIC(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Shift); void BIC(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, const ArithOption &Shift);
void ORR(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Shift); void ORR(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, const ArithOption &Shift);
void ORN(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Shift); void ORN(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, const ArithOption &Shift);
void EOR(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Shift); void EOR(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, const ArithOption &Shift);
void EON(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Shift); void EON(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, const ArithOption &Shift);
void ANDS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Shift); void ANDS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, const ArithOption &Shift);
void BICS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Shift); void BICS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, const ArithOption &Shift);
void TST(ARM64Reg Rn, ARM64Reg Rm, ArithOption Shift); void TST(ARM64Reg Rn, ARM64Reg Rm, const ArithOption &Shift);
// Wrap the above for saner syntax // Wrap the above for saner syntax
void AND(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm) { AND(Rd, Rn, Rm, ArithOption(Rd, ST_LSL, 0)); } void AND(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm) { AND(Rd, Rn, Rm, ArithOption(Rd, ST_LSL, 0)); }
@ -581,7 +581,7 @@ public:
void TST(ARM64Reg Rn, ARM64Reg Rm) { TST(Rn, Rm, ArithOption(Is64Bit(Rn) ? ZR : WZR, ST_LSL, 0)); } void TST(ARM64Reg Rn, ARM64Reg Rm) { TST(Rn, Rm, ArithOption(Is64Bit(Rn) ? ZR : WZR, ST_LSL, 0)); }
// Convenience wrappers around ORR. These match the official convenience syntax. // Convenience wrappers around ORR. These match the official convenience syntax.
void MOV(ARM64Reg Rd, ARM64Reg Rm, ArithOption Shift); void MOV(ARM64Reg Rd, ARM64Reg Rm, const ArithOption &Shift);
void MOV(ARM64Reg Rd, ARM64Reg Rm); void MOV(ARM64Reg Rd, ARM64Reg Rm);
void MVN(ARM64Reg Rd, ARM64Reg Rm); void MVN(ARM64Reg Rd, ARM64Reg Rm);
@ -681,16 +681,16 @@ public:
void LDRSW(IndexType type, ARM64Reg Rt, ARM64Reg Rn, s32 imm); void LDRSW(IndexType type, ARM64Reg Rt, ARM64Reg Rn, s32 imm);
// Load/Store register (register offset) // Load/Store register (register offset)
void STRB(ARM64Reg Rt, ARM64Reg Rn, ArithOption Rm); void STRB(ARM64Reg Rt, ARM64Reg Rn, const ArithOption &Rm);
void LDRB(ARM64Reg Rt, ARM64Reg Rn, ArithOption Rm); void LDRB(ARM64Reg Rt, ARM64Reg Rn, const ArithOption &Rm);
void LDRSB(ARM64Reg Rt, ARM64Reg Rn, ArithOption Rm); void LDRSB(ARM64Reg Rt, ARM64Reg Rn, const ArithOption &Rm);
void STRH(ARM64Reg Rt, ARM64Reg Rn, ArithOption Rm); void STRH(ARM64Reg Rt, ARM64Reg Rn, const ArithOption &Rm);
void LDRH(ARM64Reg Rt, ARM64Reg Rn, ArithOption Rm); void LDRH(ARM64Reg Rt, ARM64Reg Rn, const ArithOption &Rm);
void LDRSH(ARM64Reg Rt, ARM64Reg Rn, ArithOption Rm); void LDRSH(ARM64Reg Rt, ARM64Reg Rn, const ArithOption &Rm);
void STR(ARM64Reg Rt, ARM64Reg Rn, ArithOption Rm); void STR(ARM64Reg Rt, ARM64Reg Rn, const ArithOption &Rm);
void LDR(ARM64Reg Rt, ARM64Reg Rn, ArithOption Rm); void LDR(ARM64Reg Rt, ARM64Reg Rn, const ArithOption &Rm);
void LDRSW(ARM64Reg Rt, ARM64Reg Rn, ArithOption Rm); void LDRSW(ARM64Reg Rt, ARM64Reg Rn, const ArithOption &Rm);
void PRFM(ARM64Reg Rt, ARM64Reg Rn, ArithOption Rm); void PRFM(ARM64Reg Rt, ARM64Reg Rn, const ArithOption &Rm);
// Load/Store register (unscaled offset) // Load/Store register (unscaled offset)
void STURB(ARM64Reg Rt, ARM64Reg Rn, s32 imm); void STURB(ARM64Reg Rt, ARM64Reg Rn, s32 imm);
@ -811,8 +811,8 @@ public:
void STP(u8 size, IndexType type, ARM64Reg Rt, ARM64Reg Rt2, ARM64Reg Rn, s32 imm); void STP(u8 size, IndexType type, ARM64Reg Rt, ARM64Reg Rt2, ARM64Reg Rn, s32 imm);
// Loadstore register offset // Loadstore register offset
void STR(u8 size, ARM64Reg Rt, ARM64Reg Rn, ArithOption Rm); void STR(u8 size, ARM64Reg Rt, ARM64Reg Rn, const ArithOption &Rm);
void LDR(u8 size, ARM64Reg Rt, ARM64Reg Rn, ArithOption Rm); void LDR(u8 size, ARM64Reg Rt, ARM64Reg Rn, const ArithOption &Rm);
// Scalar - 1 Source // Scalar - 1 Source
void FABS(ARM64Reg Rd, ARM64Reg Rn); void FABS(ARM64Reg Rd, ARM64Reg Rn);
@ -1040,7 +1040,7 @@ private:
void EmitConvertScalarToInt(ARM64Reg Rd, ARM64Reg Rn, RoundingMode round, bool sign); void EmitConvertScalarToInt(ARM64Reg Rd, ARM64Reg Rn, RoundingMode round, bool sign);
void EmitScalar3Source(bool isDouble, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ARM64Reg Ra, int opcode); void EmitScalar3Source(bool isDouble, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ARM64Reg Ra, int opcode);
void EncodeLoadStorePair(u32 size, bool load, IndexType type, ARM64Reg Rt, ARM64Reg Rt2, ARM64Reg Rn, s32 imm); void EncodeLoadStorePair(u32 size, bool load, IndexType type, ARM64Reg Rt, ARM64Reg Rt2, ARM64Reg Rn, s32 imm);
void EncodeLoadStoreRegisterOffset(u32 size, bool load, ARM64Reg Rt, ARM64Reg Rn, ArithOption Rm); void EncodeLoadStoreRegisterOffset(u32 size, bool load, ARM64Reg Rt, ARM64Reg Rn, const ArithOption &Rm);
void EncodeModImm(bool Q, u8 op, u8 cmode, u8 o2, ARM64Reg Rd, u8 abcdefgh); void EncodeModImm(bool Q, u8 op, u8 cmode, u8 o2, ARM64Reg Rd, u8 abcdefgh);
void SSHLL(u8 src_size, ARM64Reg Rd, ARM64Reg Rn, u32 shift, bool upper); void SSHLL(u8 src_size, ARM64Reg Rd, ARM64Reg Rn, u32 shift, bool upper);

2
Common/Data/Text/Parsers.cpp
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@ -52,7 +52,7 @@ int Version::ToInteger() const {
return major * 1000000 + minor * 10000 + sub; return major * 1000000 + minor * 10000 + sub;
} }
bool ParseMacAddress(std::string str, uint8_t macAddr[6]) { bool ParseMacAddress(const std::string &str, uint8_t macAddr[6]) {
unsigned int mac[6]; unsigned int mac[6];
if (6 != sscanf(str.c_str(), "%02x:%02x:%02x:%02x:%02x:%02x", &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5])) { if (6 != sscanf(str.c_str(), "%02x:%02x:%02x:%02x:%02x:%02x", &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5])) {
return false; return false;

2
Common/Data/Text/Parsers.h
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@ -53,7 +53,7 @@ private:
bool ParseVersionString(std::string str); bool ParseVersionString(std::string str);
}; };
bool ParseMacAddress(std::string str, uint8_t macAddr[6]); bool ParseMacAddress(const std::string &str, uint8_t macAddr[6]);
bool TryParse(const std::string &str, bool *const output); bool TryParse(const std::string &str, bool *const output);
bool TryParse(const std::string &str, uint32_t *const output); bool TryParse(const std::string &str, uint32_t *const output);

2
Common/GPU/Vulkan/VulkanContext.cpp
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@ -486,7 +486,7 @@ bool VulkanContext::CheckLayers(const std::vector<LayerProperties> &layer_props,
return true; return true;
} }
int VulkanContext::GetPhysicalDeviceByName(std::string name) { int VulkanContext::GetPhysicalDeviceByName(const std::string &name) {
for (size_t i = 0; i < physical_devices_.size(); i++) { for (size_t i = 0; i < physical_devices_.size(); i++) {
if (physicalDeviceProperties_[i].properties.deviceName == name) if (physicalDeviceProperties_[i].properties.deviceName == name)
return (int)i; return (int)i;

2
Common/GPU/Vulkan/VulkanContext.h
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@ -180,7 +180,7 @@ public:
void DestroyInstance(); void DestroyInstance();
int GetBestPhysicalDevice(); int GetBestPhysicalDevice();
int GetPhysicalDeviceByName(std::string name); int GetPhysicalDeviceByName(const std::string &name);
void ChooseDevice(int physical_device); void ChooseDevice(int physical_device);
bool EnableInstanceExtension(const char *extension); bool EnableInstanceExtension(const char *extension);
bool EnableDeviceExtension(const char *extension); bool EnableDeviceExtension(const char *extension);

2
Common/Input/InputState.cpp
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@ -74,7 +74,7 @@ void SetInfoKeys(const std::vector<InputMapping> &info) {
infoKeys = info; infoKeys = info;
} }
void SetAnalogFlipY(std::unordered_map<InputDeviceID, int> flipYByDeviceId) { void SetAnalogFlipY(const std::unordered_map<InputDeviceID, int> &flipYByDeviceId) {
uiFlipAnalogY = flipYByDeviceId; uiFlipAnalogY = flipYByDeviceId;
} }

2
Common/Input/InputState.h
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@ -201,5 +201,5 @@ void SetTabLeftRightKeys(const std::vector<InputMapping> &tabLeft, const std::ve
void SetInfoKeys(const std::vector<InputMapping> &info); void SetInfoKeys(const std::vector<InputMapping> &info);
// 0 means unknown (attempt autodetect), -1 means flip, 1 means original direction. // 0 means unknown (attempt autodetect), -1 means flip, 1 means original direction.
void SetAnalogFlipY(std::unordered_map<InputDeviceID, int> flipYByDeviceId); void SetAnalogFlipY(const std::unordered_map<InputDeviceID, int> &flipYByDeviceId);
int GetAnalogYDirection(InputDeviceID deviceId); int GetAnalogYDirection(InputDeviceID deviceId);

2
Common/StringUtils.cpp
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@ -60,7 +60,7 @@ const char* safe_string(const char* s) {
return s ? s : "(null)"; return s ? s : "(null)";
} }
long parseHexLong(std::string s) { long parseHexLong(const std::string &s) {
long value = 0; long value = 0;
if (s.substr(0,2) == "0x") { if (s.substr(0,2) == "0x") {

2
Common/StringUtils.h
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@ -103,7 +103,7 @@ inline size_t truncate_cpy(char(&out)[Count], const char *src) {
const char* safe_string(const char* s); const char* safe_string(const char* s);
long parseHexLong(std::string s); long parseHexLong(const std::string &s);
long parseLong(std::string s); long parseLong(std::string s);
std::string StringFromFormat(const char* format, ...); std::string StringFromFormat(const char* format, ...);
// Cheap! // Cheap!

4
Common/System/OSD.cpp
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@ -224,7 +224,7 @@ void OnScreenDisplay::ShowLeaderboardSubmitted(const std::string &title, const s
g_OSD.Show(OSDType::LEADERBOARD_SUBMITTED, title, value, 3.0f); g_OSD.Show(OSDType::LEADERBOARD_SUBMITTED, title, value, 3.0f);
} }
void OnScreenDisplay::SetProgressBar(std::string id, std::string &&message, float minValue, float maxValue, float progress, float delay) { void OnScreenDisplay::SetProgressBar(const std::string &id, std::string &&message, float minValue, float maxValue, float progress, float delay) {
_dbg_assert_(!my_isnanorinf(progress)); _dbg_assert_(!my_isnanorinf(progress));
_dbg_assert_(!my_isnanorinf(minValue)); _dbg_assert_(!my_isnanorinf(minValue));
_dbg_assert_(!my_isnanorinf(maxValue)); _dbg_assert_(!my_isnanorinf(maxValue));
@ -256,7 +256,7 @@ void OnScreenDisplay::SetProgressBar(std::string id, std::string &&message, floa
entries_.push_back(bar); entries_.push_back(bar);
} }
void OnScreenDisplay::RemoveProgressBar(std::string id, bool success, float delay_s) { void OnScreenDisplay::RemoveProgressBar(const std::string &id, bool success, float delay_s) {
std::lock_guard<std::mutex> guard(mutex_); std::lock_guard<std::mutex> guard(mutex_);
for (auto iter = entries_.begin(); iter != entries_.end(); iter++) { for (auto iter = entries_.begin(); iter != entries_.end(); iter++) {
if (iter->type == OSDType::PROGRESS_BAR && iter->id == id) { if (iter->type == OSDType::PROGRESS_BAR && iter->id == id) {

4
Common/System/OSD.h
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@ -59,8 +59,8 @@ public:
// Progress bar controls // Progress bar controls
// Set is both create and update. If you set maxValue <= minValue, you'll create an "indeterminate" progress // Set is both create and update. If you set maxValue <= minValue, you'll create an "indeterminate" progress
// bar that doesn't show a specific amount of progress. // bar that doesn't show a specific amount of progress.
void SetProgressBar(std::string id, std::string &&message, float minValue, float maxValue, float progress, float delay_s); void SetProgressBar(const std::string &id, std::string &&message, float minValue, float maxValue, float progress, float delay_s);
void RemoveProgressBar(std::string id, bool success, float delay_s); void RemoveProgressBar(const std::string &id, bool success, float delay_s);
// Call every frame to keep the sidebar visible. Otherwise it'll fade out. // Call every frame to keep the sidebar visible. Otherwise it'll fade out.
void NudgeSidebar(); void NudgeSidebar();

2
Common/UI/AsyncImageFileView.h
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@ -22,7 +22,7 @@ public:
void SetFilename(const Path &filename); void SetFilename(const Path &filename);
void SetColor(uint32_t color) { color_ = color; } void SetColor(uint32_t color) { color_ = color; }
void SetOverlayText(std::string text) { text_ = text; } void SetOverlayText(const std::string &text) { text_ = text; }
void SetFixedSize(float fixW, float fixH) { fixedSizeW_ = fixW; fixedSizeH_ = fixH; } void SetFixedSize(float fixW, float fixH) { fixedSizeW_ = fixW; fixedSizeH_ = fixH; }
void SetCanBeFocused(bool can) { canFocus_ = can; } void SetCanBeFocused(bool can) { canFocus_ = can; }

4
Common/UI/PopupScreens.h
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@ -29,10 +29,10 @@ public:
std::string GetChoiceString() const { std::string GetChoiceString() const {
return adaptor_.GetTitle(listView_->GetSelected()); return adaptor_.GetTitle(listView_->GetSelected());
} }
void SetHiddenChoices(std::set<int> hidden) { void SetHiddenChoices(const std::set<int> &hidden) {
hidden_ = hidden; hidden_ = hidden;
} }
void SetChoiceIcons(std::map<int, ImageID> icons) { void SetChoiceIcons(const std::map<int, ImageID> &icons) {
icons_ = icons; icons_ = icons;
} }
const char *tag() const override { return "listpopup"; } const char *tag() const override { return "listpopup"; }