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Common: Maintain C++11 support in sign extend.

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Unknown W. Brackets 2021-01-31 08:39:21 -08:00
parent 1b00da2f3a
commit 5d60fa0d0d
23 changed files with 73 additions and 60 deletions
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2
Common/ColorConv.cpp
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@ -489,7 +489,7 @@ void ConvertRGBA5551ToBGRA8888(u32 *dst, const u16 *src, u32 numPixels) {
u32 g = Convert5To8((c >> 5) & 0x001f);
u32 b = Convert5To8((c >> 10) & 0x001f);
// We force an arithmetic shift to get the sign bits.
u32 a = SignExtend16To32(c) & 0xff000000;
u32 a = SignExtend16ToU32(c) & 0xff000000;
dst[x] = a | (r << 16) | (g << 8) | b;
}

22
Common/Data/Convert/SmallDataConvert.h
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@ -181,15 +181,21 @@ inline uint32_t BytesToUint32(uint8_t a, uint8_t b, uint8_t c, uint8_t d) {
return (a) | (b << 8) | (c << 16) | (d << 24);
}
constexpr uint32_t SignExtend8To32(uint32_t value) {
constexpr int32_t SignExtend8ToS32(uint32_t value) {
// This extends this sign at the 8th bit to the other 24 bits.
int32_t signedValue = (int8_t)(value & 0xFF);
// We return as unsigned because we're likely just interested in the bits.
return (uint32_t)signedValue;
return (int8_t)(value & 0xFF);
}
constexpr uint32_t SignExtend16To32(uint32_t value) {
// Same as SignExtend8to32, but from the 16th bit.
int32_t signedValue = (int16_t)(value & 0xFFFF);
return (uint32_t)signedValue;
constexpr uint32_t SignExtend8ToU32(uint32_t value) {
// Just treat the bits as unsigned.
return (uint32_t)SignExtend8ToS32(value);
}
constexpr int32_t SignExtend16ToS32(uint32_t value) {
// Same as SignExtend8toS32, but from the 16th bit.
return (int16_t)(value & 0xFFFF);
}
constexpr uint32_t SignExtend16ToU32(uint32_t value) {
return (uint32_t)SignExtend16ToS32(value);
}

2
Core/HLE/sceKernelModule.cpp
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@ -626,7 +626,7 @@ static void WriteVarSymbol(WriteVarSymbolState &state, u32 exportAddress, u32 re
case R_MIPS_LO16:
{
// Sign extend the existing low value (e.g. from addiu.)
const u32 offsetLo = SignExtend16To32(relocData);
const u32 offsetLo = SignExtend16ToU32(relocData);
u32 full = exportAddress;
// This is only used in the error case (no hi/wrong hi.)
if (!reverse) {

10
Core/MIPS/ARM/ArmCompALU.cpp
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@ -77,8 +77,8 @@ namespace MIPSComp
{
CONDITIONAL_DISABLE(ALU_IMM);
u32 uimm = op & 0xFFFF;
u32 suimm = SignExtend16To32(op);
s32 simm = (s32)suimm;
s32 simm = SignExtend16ToS32(op);
u32 suimm = SignExtend16ToU32(op);
MIPSGPReg rt = _RT;
MIPSGPReg rs = _RS;
@ -602,9 +602,9 @@ namespace MIPSComp
return;
switch ((op >> 6) & 31) {
case 16: // seb // R(rd) = SignExtend8To32(R(rt));
case 16: // seb // R(rd) = SignExtend8ToU32(R(rt));
if (gpr.IsImm(rt)) {
gpr.SetImm(rd, SignExtend8To32(gpr.GetImm(rt)));
gpr.SetImm(rd, SignExtend8ToU32(gpr.GetImm(rt)));
return;
}
gpr.MapDirtyIn(rd, rt);
@ -613,7 +613,7 @@ namespace MIPSComp
case 24: // seh
if (gpr.IsImm(rt)) {
gpr.SetImm(rd, SignExtend16To32(gpr.GetImm(rt)));
gpr.SetImm(rd, SignExtend16ToU32(gpr.GetImm(rt)));
return;
}
gpr.MapDirtyIn(rd, rt);

2
Core/MIPS/ARM/ArmCompBranch.cpp
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@ -49,7 +49,7 @@
#define _POS ((op>> 6) & 0x1F)
#define _SIZE ((op>>11) & 0x1F)
#define _IMM26 (op & 0x03FFFFFF)
#define TARGET16 ((int)(SignExtend16To32(op) << 2))
#define TARGET16 ((int)(SignExtend16ToU32(op) << 2))
#define TARGET26 (_IMM26 << 2)
#define LOOPOPTIMIZATION 0

2
Core/MIPS/ARM/ArmCompVFPU.cpp
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@ -2088,7 +2088,7 @@ namespace MIPSComp
u8 dreg;
GetVectorRegs(&dreg, V_Single, _VT);
s32 imm = (s32)SignExtend16To32(op);
s32 imm = SignExtend16ToS32(op);
fpr.MapRegV(dreg, MAP_DIRTY | MAP_NOINIT);
MOVI2F(fpr.V(dreg), (float)imm, SCRATCHREG1);

2
Core/MIPS/ARM/ArmCompVFPUNEON.cpp
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@ -1348,7 +1348,7 @@ void ArmJit::CompNEON_Viim(MIPSOpcode op) {
DestARMReg vt = NEONMapPrefixD(_VT, V_Single, MAP_NOINIT | MAP_DIRTY);
s32 imm = (s32)SignExtend16To32(op);
s32 imm = SignExtend16ToS32(op);
// TODO: Optimize for low registers.
MOVI2F(S0, (float)imm, R0);
VMOV_neon(vt.rd, D0);

10
Core/MIPS/ARM64/Arm64CompALU.cpp
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@ -74,8 +74,8 @@ void Arm64Jit::CompImmLogic(MIPSGPReg rs, MIPSGPReg rt, u32 uimm, void (ARM64XEm
void Arm64Jit::Comp_IType(MIPSOpcode op) {
CONDITIONAL_DISABLE(ALU_IMM);
u32 uimm = op & 0xFFFF;
u32 suimm = SignExtend16To32(op);
s32 simm = (s32)suimm;
s32 simm = SignExtend16ToS32(op);
u32 suimm = SignExtend16ToU32(op);
MIPSGPReg rt = _RT;
MIPSGPReg rs = _RS;
@ -489,9 +489,9 @@ void Arm64Jit::Comp_Allegrex(MIPSOpcode op) {
return;
switch ((op >> 6) & 31) {
case 16: // seb // R(rd) = SignExtend8To32(R(rt));
case 16: // seb // R(rd) = SignExtend8ToU32(R(rt));
if (gpr.IsImm(rt)) {
gpr.SetImm(rd, SignExtend8To32(gpr.GetImm(rt)));
gpr.SetImm(rd, SignExtend8ToU32(gpr.GetImm(rt)));
return;
}
gpr.MapDirtyIn(rd, rt);
@ -500,7 +500,7 @@ void Arm64Jit::Comp_Allegrex(MIPSOpcode op) {
case 24: // seh
if (gpr.IsImm(rt)) {
gpr.SetImm(rd, SignExtend16To32(gpr.GetImm(rt)));
gpr.SetImm(rd, SignExtend16ToU32(gpr.GetImm(rt)));
return;
}
gpr.MapDirtyIn(rd, rt);

2
Core/MIPS/ARM64/Arm64CompBranch.cpp
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@ -49,7 +49,7 @@
#define _POS ((op>> 6) & 0x1F)
#define _SIZE ((op>>11) & 0x1F)
#define _IMM26 (op & 0x03FFFFFF)
#define TARGET16 ((int)(SignExtend16To32(op) << 2))
#define TARGET16 ((int)(SignExtend16ToU32(op) << 2))
#define TARGET26 (_IMM26 << 2)
#define LOOPOPTIMIZATION 0

2
Core/MIPS/ARM64/Arm64CompVFPU.cpp
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@ -1812,7 +1812,7 @@ namespace MIPSComp {
u8 dreg;
GetVectorRegs(&dreg, V_Single, _VT);
s32 imm = (s32)SignExtend16To32(op);
s32 imm = SignExtend16ToS32(op);
fpr.MapRegV(dreg, MAP_DIRTY | MAP_NOINIT);
fp.MOVI2F(fpr.V(dreg), (float)imm, SCRATCH1);

6
Core/MIPS/IR/IRCompALU.cpp
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@ -47,9 +47,9 @@ namespace MIPSComp {
void IRFrontend::Comp_IType(MIPSOpcode op) {
CONDITIONAL_DISABLE(ALU_IMM);
s32 simm = (s32)_IMM16; // sign extension
u32 uimm = (u16)_IMM16;
u32 suimm = (u32)(s32)simm;
s32 simm = SignExtend16ToS32(op);
u32 suimm = SignExtend16ToU32(op);
MIPSGPReg rt = _RT;
MIPSGPReg rs = _RS;
@ -274,7 +274,7 @@ void IRFrontend::Comp_Allegrex(MIPSOpcode op) {
return;
switch ((op >> 6) & 31) {
case 16: // seb // R(rd) = SignExtend8To32(R(rt));
case 16: // seb // R(rd) = SignExtend8ToU32(R(rt));
ir.Write(IROp::Ext8to32, rd, rt);
break;

2
Core/MIPS/IR/IRCompBranch.cpp
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@ -42,7 +42,7 @@
#define _POS ((op>> 6) & 0x1F)
#define _SIZE ((op>>11) & 0x1F)
#define _IMM26 (op & 0x03FFFFFF)
#define TARGET16 ((int)(SignExtend16To32(op) << 2))
#define TARGET16 ((int)(SignExtend16ToU32(op) << 2))
#define TARGET26 (_IMM26 << 2)
#define LOOPOPTIMIZATION 0

2
Core/MIPS/IR/IRCompVFPU.cpp
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@ -1778,7 +1778,7 @@ namespace MIPSComp {
// Vector integer immediate
// d[0] = float(imm)
s32 imm = (s32)SignExtend16To32(op);
s32 imm = SignExtend16ToS32(op);
u8 dreg;
GetVectorRegsPrefixD(&dreg, V_Single, _VT);
ir.Write(IROp::SetConstF, dreg, ir.AddConstantFloat((float)imm));

8
Core/MIPS/IR/IRInterpreter.cpp
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@ -127,10 +127,10 @@ u32 IRInterpret(MIPSState *mips, const IRInst *inst, int count) {
mips->r[inst->dest] = ~mips->r[inst->src1];
break;
case IROp::Ext8to32:
mips->r[inst->dest] = SignExtend8To32(mips->r[inst->src1]);
mips->r[inst->dest] = SignExtend8ToU32(mips->r[inst->src1]);
break;
case IROp::Ext16to32:
mips->r[inst->dest] = SignExtend16To32(mips->r[inst->src1]);
mips->r[inst->dest] = SignExtend16ToU32(mips->r[inst->src1]);
break;
case IROp::ReverseBits:
mips->r[inst->dest] = ReverseBits32(mips->r[inst->src1]);
@ -140,13 +140,13 @@ u32 IRInterpret(MIPSState *mips, const IRInst *inst, int count) {
mips->r[inst->dest] = Memory::ReadUnchecked_U8(mips->r[inst->src1] + inst->constant);
break;
case IROp::Load8Ext:
mips->r[inst->dest] = SignExtend8To32(Memory::ReadUnchecked_U8(mips->r[inst->src1] + inst->constant));
mips->r[inst->dest] = SignExtend8ToU32(Memory::ReadUnchecked_U8(mips->r[inst->src1] + inst->constant));
break;
case IROp::Load16:
mips->r[inst->dest] = Memory::ReadUnchecked_U16(mips->r[inst->src1] + inst->constant);
break;
case IROp::Load16Ext:
mips->r[inst->dest] = SignExtend16To32(Memory::ReadUnchecked_U16(mips->r[inst->src1] + inst->constant));
mips->r[inst->dest] = SignExtend16ToU32(Memory::ReadUnchecked_U16(mips->r[inst->src1] + inst->constant));
break;
case IROp::Load32:
mips->r[inst->dest] = Memory::ReadUnchecked_U32(mips->r[inst->src1] + inst->constant);

4
Core/MIPS/IR/IRPassSimplify.cpp
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@ -37,8 +37,8 @@ u32 Evaluate(u32 a, IROp op) {
case IROp::Neg: return -(s32)a;
case IROp::BSwap16: return ((a & 0xFF00FF00) >> 8) | ((a & 0x00FF00FF) << 8);
case IROp::BSwap32: return swap32(a);
case IROp::Ext8to32: return SignExtend8To32(a);
case IROp::Ext16to32: return SignExtend16To32(a);
case IROp::Ext8to32: return SignExtend8ToU32(a);
case IROp::Ext16to32: return SignExtend16ToU32(a);
case IROp::ReverseBits: return ReverseBits32(a);
case IROp::Clz: {
int x = 31;

3
Core/MIPS/MIPSCodeUtils.cpp
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@ -28,9 +28,8 @@ namespace MIPSCodeUtils
#define OP_SYSCALL_MASK 0xFC00003F
#define _RS ((op>>21) & 0x1F)
#define _RT ((op>>16) & 0x1F)
#define _IMM16 (signed short)(op & 0xFFFF)
#define _IMM26 (op & 0x03FFFFFF)
#define TARGET16 ((int)((uint32_t)(int)_IMM16 << 2))
#define TARGET16 ((int)(SignExtend16ToU32(op) << 2))
#define TARGET26 (_IMM26 << 2)
u32 GetJumpTarget(u32 addr) {

16
Core/MIPS/MIPSCodeUtils.h
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@ -53,12 +53,20 @@
#define MIPS_GET_VS(op) ((op>>8) & 0x7F)
#define MIPS_GET_VT(op) ((op>>16) & 0x7F)
inline uint32_t SignExtend8To32(MIPSOpcode op) {
return SignExtend8To32(op.encoding);
inline int32_t SignExtend8ToS32(MIPSOpcode op) {
return SignExtend8ToS32(op.encoding);
}
inline uint32_t SignExtend16To32(MIPSOpcode op) {
return SignExtend16To32(op.encoding);
inline uint32_t SignExtend8ToU32(MIPSOpcode op) {
return SignExtend8ToU32(op.encoding);
}
inline int32_t SignExtend16ToS32(MIPSOpcode op) {
return SignExtend16ToS32(op.encoding);
}
inline uint32_t SignExtend16ToU32(MIPSOpcode op) {
return SignExtend16ToU32(op.encoding);
}
namespace MIPSCodeUtils

4
Core/MIPS/MIPSDis.cpp
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@ -173,8 +173,8 @@ namespace MIPSDis
void Dis_IType(MIPSOpcode op, char *out)
{
u32 uimm = op & 0xFFFF;
u32 suimm = SignExtend16To32(op);
s32 simm = (s32)suimm;
u32 suimm = SignExtend16ToU32(op);
s32 simm = SignExtend16ToS32(op);
int rt = _RT;
int rs = _RS;

12
Core/MIPS/MIPSInt.cpp
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@ -298,8 +298,8 @@ namespace MIPSInt
void Int_IType(MIPSOpcode op)
{
u32 uimm = op & 0xFFFF;
u32 suimm = SignExtend16To32(op);
s32 simm = (s32)suimm;
u32 suimm = SignExtend16ToU32(op);
s32 simm = SignExtend16ToS32(op);
int rt = _RT;
int rs = _RS;
@ -412,8 +412,8 @@ namespace MIPSInt
switch (op >> 26)
{
case 32: R(rt) = SignExtend8To32(Memory::Read_U8(addr)); break; //lb
case 33: R(rt) = SignExtend16To32(Memory::Read_U16(addr)); break; //lh
case 32: R(rt) = SignExtend8ToU32(Memory::Read_U8(addr)); break; //lb
case 33: R(rt) = SignExtend16ToU32(Memory::Read_U16(addr)); break; //lh
case 35: R(rt) = Memory::Read_U32(addr); break; //lw
case 36: R(rt) = Memory::Read_U8 (addr); break; //lbu
case 37: R(rt) = Memory::Read_U16(addr); break; //lhu
@ -739,7 +739,7 @@ namespace MIPSInt
switch((op>>6)&31)
{
case 16: // seb
R(rd) = SignExtend8To32(R(rt));
R(rd) = SignExtend8ToU32(R(rt));
break;
case 20: // bitrev
@ -757,7 +757,7 @@ namespace MIPSInt
break;
case 24: // seh
R(rd) = SignExtend16To32(R(rt));
R(rd) = SignExtend16ToU32(R(rt));
break;
default:

12
Core/MIPS/x86/CompALU.cpp
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@ -78,9 +78,9 @@ namespace MIPSComp
void Jit::Comp_IType(MIPSOpcode op)
{
CONDITIONAL_DISABLE(ALU_IMM);
s32 simm = (s32)_IMM16; // sign extension
u32 uimm = op & 0xFFFF;
u32 suimm = (u32)(s32)simm;
s32 simm = SignExtend16ToS32(op);
u32 suimm = SignExtend16ToU32(op);
MIPSGPReg rt = _RT;
MIPSGPReg rs = _RS;
@ -798,10 +798,10 @@ namespace MIPSComp
switch ((op >> 6) & 31)
{
case 16: // seb // R(rd) = SignExtend8To32(R(rt));
case 16: // seb // R(rd) = SignExtend8ToU32(R(rt));
if (gpr.IsImm(rt))
{
gpr.SetImm(rd, SignExtend8To32(gpr.GetImm(rt)));
gpr.SetImm(rd, SignExtend8ToU32(gpr.GetImm(rt)));
break;
}
@ -876,10 +876,10 @@ namespace MIPSComp
gpr.UnlockAll();
break;
case 24: // seh // R(rd) = SignExtend16To32(R(rt));
case 24: // seh // R(rd) = SignExtend16ToU32(R(rt));
if (gpr.IsImm(rt))
{
gpr.SetImm(rd, SignExtend16To32(gpr.GetImm(rt)));
gpr.SetImm(rd, SignExtend16ToU32(gpr.GetImm(rt)));
break;
}

2
Core/MIPS/x86/CompBranch.cpp
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@ -48,7 +48,7 @@
#define _POS ((op>> 6) & 0x1F)
#define _SIZE ((op>>11) & 0x1F)
#define _IMM26 (op & 0x03FFFFFF)
#define TARGET16 ((int)(SignExtend16To32(op) << 2))
#define TARGET16 ((int)(SignExtend16ToU32(op) << 2))
#define TARGET26 (_IMM26 << 2)
#define LOOPOPTIMIZATION 0

4
Core/MIPS/x86/CompLoadStore.cpp
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@ -309,11 +309,11 @@ namespace MIPSComp {
CompITypeMemRead(op, 32, &XEmitter::MOVZX, safeMemFuncs.readU32);
break;
case 32: //R(rt) = SignExtend8To32 (ReadMem8 (addr)); break; //lb
case 32: //R(rt) = SignExtend8ToU32 (ReadMem8 (addr)); break; //lb
CompITypeMemRead(op, 8, &XEmitter::MOVSX, safeMemFuncs.readU8);
break;
case 33: //R(rt) = SignExtend16To32(ReadMem16(addr)); break; //lh
case 33: //R(rt) = SignExtend16ToU32(ReadMem16(addr)); break; //lh
CompITypeMemRead(op, 16, &XEmitter::MOVSX, safeMemFuncs.readU16);
break;

2
Core/MIPS/x86/CompVFPU.cpp
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@ -3452,7 +3452,7 @@ void Jit::Comp_Viim(MIPSOpcode op) {
// Flush SIMD.
fpr.SimpleRegsV(&dreg, V_Single, MAP_NOINIT | MAP_DIRTY);
s32 imm = (s32)SignExtend16To32(op);
s32 imm = SignExtend16ToS32(op);
FP32 fp;
fp.f = (float)imm;
MOV(32, R(TEMPREG), Imm32(fp.u));