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More disassembly improvements
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parent
779272e7f5
commit
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@ -343,6 +343,15 @@ instr_disassemble(word instr, address addr, pDisOptions opts) {
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if (instr&Sbit) *flagp++='S';
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break;
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case 1:
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if ((instr & 0x0FFFFFF0) == ((18 << 20) | (0xFFF << 8) | (1 << 4))) {
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mnemonic = "B";
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format = "0";
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break;
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} else if ((instr & 0x0FFFFFF0) == 0x12FFF30) {
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mnemonic = "BL";
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format = "0";
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break;
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}
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case 3:
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/* SWP or MRS/MSR or data processing */
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// hrydgard addition: MOVW/MOVT
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@ -671,7 +680,7 @@ lUndefined:
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result.is_SWI = 1;
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result.swinum = instr&0x00FFFFFF;
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result.addrstart = op;
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op += sprintf(op, "&%lX", result.swinum);
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op += sprintf(op, "&%X", result.swinum);
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break;
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case '%':
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*op++='{';
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@ -933,13 +942,17 @@ static sDisOptions options = {
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reg_names
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};
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const char *ArmRegName(int r) {
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return reg_names[r];
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}
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void ArmDis(unsigned int addr, unsigned int w, char *output) {
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pInstruction instr = instr_disassemble(w, addr, &options);
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sprintf(output, "%.6lX %.8lX\t%s", addr, w, instr->text);
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sprintf(output, "%08x\t%s", w, instr->text);
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if (instr->undefined || instr->badbits || instr->oddbits) {
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if (instr->undefined) sprintf(output, " [undefined instr %08x]", w);
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if (instr->badbits) sprintf(output, " [illegal bits %08x]", w);
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if (instr->oddbits) sprintf(output, " [unexpected bits %08x]", w);
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strcat(output, " ? (extra bits)");
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//if (instr->oddbits) sprintf(output, " [unexpected bits %08x]", w);
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}
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// zap tabs
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while (*output) {
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@ -30,4 +30,5 @@
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// The only changes I've done is C++ compat and replaced the main
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// program with this function.
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const char *ArmRegName(int r);
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void ArmDis(unsigned int addr, unsigned int w, char *output);
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