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irjit: Add a pass to keep Vec4s in Vec4s.
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@ -281,6 +281,7 @@ void IRFrontend::DoJit(u32 em_address, std::vector<IRInst> &instructions, u32 &m
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&OptimizeFPMoves,
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&PropagateConstants,
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&PurgeTemps,
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&ReduceVec4Flush,
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// &ReorderLoadStore,
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// &MergeLoadStore,
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// &ThreeOpToTwoOp,
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@ -6,6 +6,7 @@
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#include "Common/Data/Convert/SmallDataConvert.h"
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#include "Common/Log.h"
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#include "Core/Config.h"
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#include "Core/MIPS/MIPSVFPUUtils.h"
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#include "Core/MIPS/IR/IRAnalysis.h"
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#include "Core/MIPS/IR/IRInterpreter.h"
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#include "Core/MIPS/IR/IRPassSimplify.h"
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@ -1874,3 +1875,218 @@ bool ApplyMemoryValidation(const IRWriter &in, IRWriter &out, const IROptions &o
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}
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return logBlocks;
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}
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bool ReduceVec4Flush(const IRWriter &in, IRWriter &out, const IROptions &opts) {
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CONDITIONAL_DISABLE;
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// Only do this when using a SIMD backend.
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if (!opts.preferVec4) {
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DISABLE;
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}
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bool isVec4[256]{};
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bool isUsed[256]{};
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bool isVec4Dirty[256]{};
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auto updateVec4 = [&](char type, IRReg r) {
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bool downgraded = false;
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switch (type) {
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case 'F':
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downgraded = isVec4[r & ~3];
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isVec4[r & ~3] = false;
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isUsed[r] = true;
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break;
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case 'V':
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_dbg_assert_((r & 3) == 0);
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isVec4[r] = true;
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for (int i = 0; i < 4; ++i)
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isUsed[r + i] = true;
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break;
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case '2':
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downgraded = isVec4[r & ~3];
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isVec4[r & ~3] = false;
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for (int i = 0; i < 2; ++i)
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isUsed[r + i] = true;
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break;
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default:
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break;
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}
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return downgraded;
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};
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auto updateVec4Dest = [&](char type, IRReg r, uint32_t flags) {
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if ((flags & IRFLAG_SRC3) == 0) {
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switch (type) {
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case 'F':
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isVec4Dirty[r & ~3] = false;
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break;
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case 'V':
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_dbg_assert_((r & 3) == 0);
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isVec4Dirty[r] = true;
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break;
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case '2':
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isVec4Dirty[r & ~3] = false;
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break;
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default:
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break;
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}
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}
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return updateVec4(type, r);
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};
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// Checks overlap from r1 to other params.
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auto overlapped = [](IRReg r1, int l1, IRReg r2, int l2, IRReg r3 = IRREG_INVALID, int l3 = 0) {
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if (r1 < r2 + l2 && r1 + l1 > r2)
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return true;
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if (r1 < r3 + l3 && r1 + l1 > r3)
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return true;
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return false;
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};
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bool logBlocks = false;
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int inCount = (int)in.GetInstructions().size();
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for (int i = 0; i < inCount; ++i) {
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IRInst inst = in.GetInstructions()[i];
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const IRMeta *m = GetIRMeta(inst.op);
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if ((m->flags & (IRFLAG_EXIT | IRFLAG_BARRIER)) != 0) {
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memset(isVec4, 0, sizeof(isVec4));
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out.Write(inst);
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continue;
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}
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IRReg temp = IRREG_INVALID;
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auto findAvailTempVec4 = [&]() {
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// If it's not used yet in this block, we can use it.
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// Note: even if the instruction uses it to write, that should be fine.
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for (IRReg r = IRVTEMP_PFX_S; r < IRVTEMP_0 + 4; r += 4) {
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if (isUsed[r])
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continue;
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bool usable = true;
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for (int j = 1; j < 4; ++j)
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usable = usable && !isUsed[r + j];
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if (usable) {
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temp = r;
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// We don't update isUsed because our temporary doesn't need to last.
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return true;
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}
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}
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return false;
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};
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switch (inst.op) {
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case IROp::SetConstF:
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if (isVec4[inst.dest & ~3] && findAvailTempVec4()) {
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// Check if we're setting multiple in a row, this is a bit common.
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u8 blendMask = 1 << (inst.dest & 3);
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while (i + 1 < inCount) {
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IRInst next = in.GetInstructions()[i + 1];
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if (next.op != IROp::SetConstF || (next.dest & ~3) != (inst.dest & ~3))
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break;
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if (next.constant != inst.constant)
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break;
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blendMask |= 1 << (next.dest & 3);
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i++;
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}
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if (inst.constant == 0) {
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out.Write(IROp::Vec4Init, temp, (int)Vec4Init::AllZERO);
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} else if (inst.constant == 0x3F800000) {
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out.Write(IROp::Vec4Init, temp, (int)Vec4Init::AllONE);
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} else if (inst.constant == 0xBF800000) {
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out.Write(IROp::Vec4Init, temp, (int)Vec4Init::AllMinusONE);
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} else {
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out.Write(IROp::SetConstF, temp, out.AddConstant(inst.constant));
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out.Write(IROp::Vec4Shuffle, temp, temp, 0);
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}
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out.Write(IROp::Vec4Blend, inst.dest & ~3, inst.dest & ~3, temp, blendMask);
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isVec4Dirty[inst.dest & ~3] = true;
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continue;
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}
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break;
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case IROp::FMovFromGPR:
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if (isVec4[inst.dest & ~3] && findAvailTempVec4()) {
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u8 blendMask = 1 << (inst.dest & 3);
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out.Write(IROp::FMovFromGPR, temp, inst.src1);
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out.Write(IROp::Vec4Shuffle, temp, temp, 0);
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out.Write(IROp::Vec4Blend, inst.dest & ~3, inst.dest & ~3, temp, blendMask);
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isVec4Dirty[inst.dest & ~3] = true;
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continue;
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}
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break;
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case IROp::LoadFloat:
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if (isVec4[inst.dest & ~3] && isVec4Dirty[inst.dest & ~3] && findAvailTempVec4()) {
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u8 blendMask = 1 << (inst.dest & 3);
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out.Write(inst.op, temp, inst.src1, inst.src2, inst.constant);
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out.Write(IROp::Vec4Shuffle, temp, temp, 0);
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out.Write(IROp::Vec4Blend, inst.dest & ~3, inst.dest & ~3, temp, blendMask);
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isVec4Dirty[inst.dest & ~3] = true;
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continue;
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}
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break;
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case IROp::FMov:
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if (isVec4[inst.dest & ~3] && (inst.dest & ~3) == (inst.src1 & ~3)) {
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// Oh, actually a shuffle?
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uint8_t shuffle = (uint8_t)VFPU_SWIZZLE(0, 1, 2, 3);
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uint8_t destShift = (inst.dest & 3) * 2;
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shuffle = (shuffle & ~(3 << destShift)) | ((inst.src1 & 3) << destShift);
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out.Write(IROp::Vec4Shuffle, inst.dest & ~3, inst.dest & ~3, shuffle);
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isVec4Dirty[inst.dest & ~3] = true;
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continue;
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} else if (isVec4[inst.dest & ~3] && isVec4[inst.src1 & ~3] && (inst.dest & 3) == (inst.src1 & 3)) {
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// We can turn this directly into a blend, since it's the same lane.
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out.Write(IROp::Vec4Blend, inst.dest & ~3, inst.dest & ~3, inst.src1 & ~3, 1 << (inst.dest & 3));
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isVec4Dirty[inst.dest & ~3] = true;
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continue;
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} else if (isVec4[inst.dest & ~3] && isVec4[inst.src1 & ~3] && findAvailTempVec4()) {
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// For this, we'll need a temporary to move to the right lane.
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uint8_t shuffle = (uint8_t)VFPU_SWIZZLE(inst.src1 & 3, inst.src1 & 3, inst.src1 & 3, inst.src1 & 3);
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out.Write(IROp::Vec4Shuffle, temp, inst.src1 & ~3, shuffle);
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out.Write(IROp::Vec4Blend, inst.dest & ~3, inst.dest & ~3, temp, 1 << (inst.dest & 3));
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isVec4Dirty[inst.dest & ~3] = true;
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continue;
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}
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break;
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case IROp::FAdd:
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case IROp::FSub:
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case IROp::FMul:
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case IROp::FDiv:
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if (isVec4[inst.dest & ~3] && isVec4Dirty[inst.dest & ~3] && findAvailTempVec4()) {
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u8 blendMask = 1 << (inst.dest & 3);
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out.Write(inst.op, temp, inst.src1, inst.src2);
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out.Write(IROp::Vec4Shuffle, temp, temp, 0);
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out.Write(IROp::Vec4Blend, inst.dest & ~3, inst.dest & ~3, temp, blendMask);
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isVec4Dirty[inst.dest & ~3] = true;
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continue;
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}
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break;
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}
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bool downgrade = false;
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if (updateVec4Dest(m->types[0], inst.dest, m->flags))
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downgrade = true;
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if (updateVec4(m->types[1], inst.src1))
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downgrade = true;
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if (updateVec4(m->types[2], inst.src2))
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downgrade = true;
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if (downgrade) {
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//WARN_LOG(JIT, "Vec4 downgrade by: %s", m->name);
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}
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out.Write(inst);
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}
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return logBlocks;
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}
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@ -15,3 +15,4 @@ bool OptimizeFPMoves(const IRWriter &in, IRWriter &out, const IROptions &opts);
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bool ReorderLoadStore(const IRWriter &in, IRWriter &out, const IROptions &opts);
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bool MergeLoadStore(const IRWriter &in, IRWriter &out, const IROptions &opts);
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bool ApplyMemoryValidation(const IRWriter &in, IRWriter &out, const IROptions &opts);
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bool ReduceVec4Flush(const IRWriter &in, IRWriter &out, const IROptions &opts);
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