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Merge pull request #16305 from unknownbrackets/ir-fpu

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irjit: Fix unordered float compares
This commit is contained in:
Henrik Rydgård 2022-10-31 09:10:53 +01:00 committed by GitHub
commit 61ce0d02f2
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5 changed files with 16 additions and 8 deletions
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4
Core/MIPS/IR/IRCompALU.cpp
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@ -118,7 +118,7 @@ void IRFrontend::Comp_RType3(MIPSOpcode op) {
MIPSGPReg rd = _RD;
// noop, won't write to ZERO.
if (rd == 0)
if (rd == MIPS_REG_ZERO)
return;
switch (op & 63) {
@ -298,7 +298,7 @@ void IRFrontend::Comp_Allegrex2(MIPSOpcode op) {
MIPSGPReg rd = _RD;
// Don't change $zr.
if (rd == 0)
if (rd == MIPS_REG_ZERO)
return;
switch (op & 0x3ff) {

2
Core/MIPS/IR/IRCompFPU.cpp
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@ -118,7 +118,7 @@ void IRFrontend::Comp_FPUComp(MIPSOpcode op) {
break;
case 3: // ueq, ngl (equal, unordered)
mode = IRFpCompareMode::EqualUnordered;
return;
break;
case 4: // olt, lt (less than, ordered)
mode = IRFpCompareMode::LessOrdered;
break;

1
Core/MIPS/IR/IRCompVFPU.cpp
View File

@ -464,6 +464,7 @@ namespace MIPSComp {
init = Vec4Init::AllONE;
break;
default:
INVALIDOP;
return;
}
ir.Write(IROp::Vec4Init, vec[0], (int)init);

12
Core/MIPS/IR/IRInterpreter.cpp
View File

@ -881,17 +881,23 @@ u32 IRInterpret(MIPSState *mips, const IRInst *inst, int count) {
break;
}
case IRFpCompareMode::EqualOrdered:
case IRFpCompareMode::EqualUnordered:
mips->fpcond = mips->f[inst->src1] == mips->f[inst->src2];
break;
case IRFpCompareMode::EqualUnordered:
mips->fpcond = mips->f[inst->src1] == mips->f[inst->src2] || my_isnan(mips->f[inst->src1]) || my_isnan(mips->f[inst->src2]);
break;
case IRFpCompareMode::LessEqualOrdered:
case IRFpCompareMode::LessEqualUnordered:
mips->fpcond = mips->f[inst->src1] <= mips->f[inst->src2];
break;
case IRFpCompareMode::LessEqualUnordered:
mips->fpcond = !(mips->f[inst->src1] > mips->f[inst->src2]);
break;
case IRFpCompareMode::LessOrdered:
case IRFpCompareMode::LessUnordered:
mips->fpcond = mips->f[inst->src1] < mips->f[inst->src2];
break;
case IRFpCompareMode::LessUnordered:
mips->fpcond = !(mips->f[inst->src1] >= mips->f[inst->src2]);
break;
}
break;

5
Core/MIPS/MIPSIntVFPU.cpp
View File

@ -1629,8 +1629,9 @@ namespace MIPSInt
d[cosineLane] = cosine;
}
// D prefix works, just not for x.
currentMIPS->vfpuCtrl[VFPU_CTRL_DPREFIX] &= 0xFFEFC;
// D prefix works, just not for the cosine lane.
uint32_t dprefixRemove = (3 << cosineLane) | (1 << (8 + cosineLane));
currentMIPS->vfpuCtrl[VFPU_CTRL_DPREFIX] &= 0xFFFFF ^ dprefixRemove;
ApplyPrefixD(d, sz);
WriteVector(d, sz, vd);
PC += 4;