Add a method to save the gpr/fpr state in jit.

Core/MIPS/x86/Jit.cpp

@@ -134,6 +134,20 @@ void Jit::DoDummyState(PointerWrap &p)
 	p.DoMarker("Jit");
 }
 
+
+void Jit::GetStateAndFlushAll(RegCacheState &state)
+{
+	gpr.GetState(state.gpr);
+	fpr.GetState(state.fpr);
+	FlushAll();
+}
+
+void Jit::RestoreState(const RegCacheState state)
+{
+	gpr.RestoreState(state.gpr);
+	fpr.RestoreState(state.fpr);
+}
+
 void Jit::FlushAll()
 {
 	gpr.Flush();

Core/MIPS/x86/Jit.h

@@ -151,6 +151,12 @@ enum CompileDelaySlotFlags
 	DELAYSLOT_SAFE_FLUSH = DELAYSLOT_FLUSH | DELAYSLOT_SAFE,
 };
 
+// TODO: Hmm, humongous.
+struct RegCacheState {
+	GPRRegCacheState gpr;
+	FPURegCacheState fpr;
+};
+
 class Jit : public Gen::XCodeBlock
 {
 public:
@@ -255,6 +261,8 @@ public:
 	void ClearCache();
 	void ClearCacheAt(u32 em_address);
 private:
+	void GetStateAndFlushAll(RegCacheState &state);
+	void RestoreState(const RegCacheState state);
 	void FlushAll();
 	void FlushPrefixV();
 	void WriteDowncount(int offset = 0);

Core/MIPS/x86/RegCache.cpp

@@ -282,8 +282,7 @@ void GPRRegCache::StoreFromRegister(int i) {
 	}
 }
 
-void GPRRegCache::Flush()
-{
+void GPRRegCache::Flush() {
 	for (int i = 0; i < NUM_X_REGS; i++) {
 		if (xregs[i].allocLocked)
 			PanicAlert("Someone forgot to unlock X64 reg %i.", i);
@@ -305,4 +304,14 @@ void GPRRegCache::Flush()
 			}
 		}
 	}
-}
+}
+
+void GPRRegCache::GetState(GPRRegCacheState &state) const {
+	memcpy(state.regs, regs, sizeof(regs));
+	memcpy(state.xregs, xregs, sizeof(xregs));
+}
+
+void GPRRegCache::RestoreState(const GPRRegCacheState state) {
+	memcpy(regs, state.regs, sizeof(regs));
+	memcpy(xregs, state.xregs, sizeof(xregs));
+}

Core/MIPS/x86/RegCache.h

@@ -22,6 +22,15 @@
 
 using namespace Gen;
 
+#ifdef _M_X64
+#define NUM_X_REGS 16
+#elif _M_IX86
+#define NUM_X_REGS 8
+#endif
+
+// TODO: Add more cachable regs, like HI, LO
+#define NUM_MIPS_GPRS 32
+
 struct MIPSCachedReg {
 	OpArg location;
 	bool away;  // value not in source register
@@ -35,14 +44,10 @@ struct X64CachedReg {
 	bool allocLocked;
 };
 
-#ifdef _M_X64
-#define NUM_X_REGS 16
-#elif _M_IX86
-#define NUM_X_REGS 8
-#endif
-
-// TODO: Add more cachable regs, like HI, LO
-#define NUM_MIPS_GPRS 32
+struct GPRRegCacheState {
+	MIPSCachedReg regs[NUM_MIPS_GPRS];
+	X64CachedReg xregs[NUM_X_REGS];
+};
 
 class GPRRegCache
 {
@@ -91,6 +96,9 @@ public:
 	bool IsImmediate(int preg) const;
 	u32 GetImmediate32(int preg) const;
 
+	void GetState(GPRRegCacheState &state) const;
+	void RestoreState(const GPRRegCacheState state);
+
 	MIPSState *mips;
 
 private:

Core/MIPS/x86/RegCacheFPU.cpp

@@ -255,3 +255,13 @@ void FPURegCache::FlushX(X64Reg reg) {
 		StoreFromRegister(xregs[reg].mipsReg);
 	}
 }
+
+void FPURegCache::GetState(FPURegCacheState &state) const {
+	memcpy(state.regs, regs, sizeof(regs));
+	memcpy(state.xregs, xregs, sizeof(xregs));
+}
+
+void FPURegCache::RestoreState(const FPURegCacheState state) {
+	memcpy(regs, state.regs, sizeof(regs));
+	memcpy(xregs, state.xregs, sizeof(xregs));
+}

Core/MIPS/x86/RegCacheFPU.h

@@ -57,6 +57,11 @@ struct MIPSCachedFPReg {
 	bool tempLocked;
 };
 
+struct FPURegCacheState {
+	MIPSCachedFPReg regs[NUM_MIPS_FPRS];
+	X64CachedFPReg xregs[NUM_X_FPREGS];
+};
+
 enum {
 	MAP_DIRTY = 1,
 	MAP_NOINIT = 2,
@@ -129,6 +134,9 @@ public:
 		ReleaseSpillLock(vreg + 32);
 	}
 
+	void GetState(FPURegCacheState &state) const;
+	void RestoreState(const FPURegCacheState state);
+
 	MIPSState *mips;
 
 private: