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armjit: Fix encoding of LDRH/STRH/LDRSH/LDRSB.

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Fixes fastmem issues recently introduced.
This commit is contained in:
Unknown W. Brackets 2013-03-15 00:09:12 -07:00
parent 6a9e2e559c
commit 663b481033
1 changed files with 7 additions and 3 deletions
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10
Common/ArmEmitter.cpp
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@ -656,7 +656,7 @@ void ARMXEmitter::WriteStoreOp(u32 Op, ARMReg Rt, ARMReg Rn, Operand2 Rm, bool R
bool Index = true;
bool Add = false;
// Special Encoding
// Special Encoding (misc addressing mode)
bool SpecialOp = false;
bool Half = false;
bool SignedLoad = false;
@ -700,13 +700,17 @@ void ARMXEmitter::WriteStoreOp(u32 Op, ARMReg Rt, ARMReg Rn, Operand2 Rm, bool R
}
break;
case TYPE_REG:
Data = Rm.GetData();
Add = RegAdd;
break;
case TYPE_IMMSREG:
if (!SpecialOp)
{
Data = Rm.GetData();
Add = RegAdd;
break;
}
break;
// Intentional fallthrough: TYPE_IMMSREG not supported for misc addressing.
default:
// RSR not supported for any of these
// We already have the warning above
@ -717,7 +721,7 @@ void ARMXEmitter::WriteStoreOp(u32 Op, ARMReg Rt, ARMReg Rn, Operand2 Rm, bool R
if (SpecialOp)
{
// Add SpecialOp things
Data = (0x5 << 4) | (SignedLoad << 6) | (Half << 5) | Data;
Data = (0x9 << 4) | (SignedLoad << 6) | (Half << 5) | Data;
}
Write32(condition | (op << 20) | (Index << 24) | (Add << 23) | (Rn << 16) | (Rt << 12) | Data);
}