mirror of
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Merge pull request #18073 from unknownbrackets/arm64jit-vec4
arm64jit: Implement several other Vec4 IR ops
This commit is contained in:
Henrik Rydgård
GitHub
commit
6c3547d7ae
2
.github/workflows/build.yml
vendored
2
.github/workflows/build.yml
vendored
@ -229,6 +229,8 @@ jobs:
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- name: Setup ccache
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uses: hendrikmuhs/ccache-action@v1.2
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# Disable ccache on macos for now, it's become buggy for some reason.
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if: matrix.id != 'macos'
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with:
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key: ${{ matrix.id }}
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@ -2128,6 +2128,13 @@ void ARM64FloatEmitter::EmitCopy(bool Q, u32 op, u32 imm5, u32 imm4, ARM64Reg Rd
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(1 << 10) | (Rn << 5) | Rd);
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}
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void ARM64FloatEmitter::EmitScalarPairwise(bool U, u32 size, u32 opcode, ARM64Reg Rd, ARM64Reg Rn) {
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Rd = DecodeReg(Rd);
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Rn = DecodeReg(Rn);
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Write32((1 << 30) | (U << 29) | (0b111100011 << 20) | (size << 22) | (opcode << 12) | (1 << 11) | (Rn << 5) | Rd);
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}
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void ARM64FloatEmitter::Emit2RegMisc(bool Q, bool U, u32 size, u32 opcode, ARM64Reg Rd, ARM64Reg Rn)
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{
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_assert_msg_(!IsSingle(Rd), "%s doesn't support singles!", __FUNCTION__);
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@ -2906,6 +2913,22 @@ void ARM64FloatEmitter::FSQRT(ARM64Reg Rd, ARM64Reg Rn)
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EmitScalar1Source(0, 0, IsDouble(Rd), 3, Rd, Rn);
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}
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// Scalar - pairwise
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void ARM64FloatEmitter::FADDP(ARM64Reg Rd, ARM64Reg Rn) {
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EmitScalarPairwise(1, IsDouble(Rd), 0b01101, Rd, Rn);
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}
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void ARM64FloatEmitter::FMAXP(ARM64Reg Rd, ARM64Reg Rn) {
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EmitScalarPairwise(1, IsDouble(Rd), 0b01111, Rd, Rn);
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}
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void ARM64FloatEmitter::FMINP(ARM64Reg Rd, ARM64Reg Rn) {
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EmitScalarPairwise(1, IsDouble(Rd) ? 3 : 2, 0b01111, Rd, Rn);
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}
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void ARM64FloatEmitter::FMAXNMP(ARM64Reg Rd, ARM64Reg Rn) {
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EmitScalarPairwise(1, IsDouble(Rd), 0b01100, Rd, Rn);
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}
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void ARM64FloatEmitter::FMINNMP(ARM64Reg Rd, ARM64Reg Rn) {
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EmitScalarPairwise(1, IsDouble(Rd) ? 3 : 2, 0b01100, Rd, Rn);
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}
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// Scalar - 2 Source
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void ARM64FloatEmitter::FADD(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
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@ -3023,6 +3046,9 @@ void ARM64FloatEmitter::FADD(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
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{
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EmitThreeSame(0, size >> 6, 0x1A, Rd, Rn, Rm);
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}
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void ARM64FloatEmitter::FADDP(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm) {
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EmitThreeSame(1, size >> 6, 0x1A, Rd, Rn, Rm);
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}
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void ARM64FloatEmitter::FMAX(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
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{
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EmitThreeSame(0, size >> 6, 0x1E, Rd, Rn, Rm);
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@ -3290,6 +3316,95 @@ void ARM64FloatEmitter::SMOV(u8 size, ARM64Reg Rd, ARM64Reg Rn, u8 index)
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EmitCopy(b64Bit, 0, imm5, 5, Rd, Rn);
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}
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void ARM64FloatEmitter::EncodeModImm(bool Q, u8 op, u8 cmode, u8 o2, ARM64Reg Rd, u8 abcdefgh) {
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Rd = DecodeReg(Rd);
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u8 abc = abcdefgh >> 5;
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u8 defgh = abcdefgh & 0x1F;
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Write32((Q << 30) | (op << 29) | (0xF << 24) | (abc << 16) | (cmode << 12) | (o2 << 11) | (1 << 10) | (defgh << 5) | Rd);
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}
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void ARM64FloatEmitter::FMOV(u8 size, ARM64Reg Rd, u8 imm8) {
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_assert_msg_(!IsSingle(Rd), "%s doesn't support singles", __FUNCTION__);
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_assert_msg_(size == 32 || size == 64, "%s: unsupported size", __FUNCTION__);
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_assert_msg_(IsQuad(Rd) || size == 32, "Use non-SIMD FMOV to load one double imm8");
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EncodeModImm(IsQuad(Rd), size >> 6, 0b1111, 0, Rd, imm8);
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}
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void ARM64FloatEmitter::MOVI(u8 size, ARM64Reg Rd, u8 imm8, u8 shift, bool MSL) {
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_assert_msg_(!IsSingle(Rd), "%s doesn't support singles", __FUNCTION__);
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_assert_msg_(size == 8 || size == 16 || size == 32 || size == 64, "%s: unsupported size %d", __FUNCTION__, size);
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_assert_msg_((shift & 7) == 0 && shift < size, "%s: unsupported shift %d", __FUNCTION__, shift);
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_assert_msg_(!MSL || (size == 32 && shift > 0 && shift <= 16), "MOVI MSL shift requires size 32, shift must be 8 or 16");
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_assert_msg_(size != 64 || shift == 0, "MOVI 64-bit imm cannot be shifted");
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u8 cmode = 0;
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if (size == 8)
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cmode = 0b1110;
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else if (size == 16)
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cmode = 0b1000 | (shift >> 2);
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else if (MSL)
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cmode = 0b1100 | (shift >> 3);
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else if (size == 32)
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cmode = (shift >> 2);
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else if (size == 64)
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cmode = 0b1110;
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else
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_assert_msg_(false, "%s: unhandled case", __FUNCTION__);
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EncodeModImm(IsQuad(Rd), size >> 6, cmode, 0, Rd, imm8);
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}
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void ARM64FloatEmitter::MVNI(u8 size, ARM64Reg Rd, u8 imm8, u8 shift, bool MSL) {
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_assert_msg_(!IsSingle(Rd), "%s doesn't support singles", __FUNCTION__);
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_assert_msg_(size == 16 || size == 32, "%s: unsupported size %d", __FUNCTION__, size);
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_assert_msg_((shift & 7) == 0 && shift < size, "%s: unsupported shift %d", __FUNCTION__, shift);
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_assert_msg_(!MSL || (size == 32 && shift > 0 && shift <= 16), "MVNI MSL shift requires size 32, shift must be 8 or 16");
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u8 cmode = 0;
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if (size == 16)
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cmode = 0b1000 | (shift >> 2);
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else if (MSL)
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cmode = 0b1100 | (shift >> 3);
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else if (size == 32)
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cmode = (shift >> 2);
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else
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_assert_msg_(false, "%s: unhandled case", __FUNCTION__);
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EncodeModImm(IsQuad(Rd), 1, cmode, 0, Rd, imm8);
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}
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void ARM64FloatEmitter::ORR(u8 size, ARM64Reg Rd, u8 imm8, u8 shift) {
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_assert_msg_(!IsSingle(Rd), "%s doesn't support singles", __FUNCTION__);
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_assert_msg_(size == 16 || size == 32, "%s: unsupported size %d", __FUNCTION__, size);
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_assert_msg_((shift & 7) == 0 && shift < size, "%s: unsupported shift %d", __FUNCTION__, shift);
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u8 cmode = 0;
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if (size == 16)
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cmode = 0b1001 | (shift >> 2);
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else if (size == 32)
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cmode = 0b0001 | (shift >> 2);
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else
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_assert_msg_(false, "%s: unhandled case", __FUNCTION__);
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EncodeModImm(IsQuad(Rd), 0, cmode, 0, Rd, imm8);
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}
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void ARM64FloatEmitter::BIC(u8 size, ARM64Reg Rd, u8 imm8, u8 shift) {
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_assert_msg_(!IsSingle(Rd), "%s doesn't support singles", __FUNCTION__);
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_assert_msg_(size == 16 || size == 32, "%s: unsupported size %d", __FUNCTION__, size);
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_assert_msg_((shift & 7) == 0 && shift < size, "%s: unsupported shift %d", __FUNCTION__, shift);
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u8 cmode = 0;
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if (size == 16)
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cmode = 0b1001 | (shift >> 2);
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else if (size == 32)
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cmode = 0b0001 | (shift >> 2);
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else
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_assert_msg_(false, "%s: unhandled case", __FUNCTION__);
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EncodeModImm(IsQuad(Rd), 1, cmode, 0, Rd, imm8);
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}
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// One source
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void ARM64FloatEmitter::FCVT(u8 size_to, u8 size_from, ARM64Reg Rd, ARM64Reg Rn)
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{
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@ -3918,17 +4033,32 @@ void ARM64FloatEmitter::MOVI2F(ARM64Reg Rd, float value, ARM64Reg scratch, bool
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}
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// TODO: Quite a few values could be generated easily using the MOVI instruction and friends.
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void ARM64FloatEmitter::MOVI2FDUP(ARM64Reg Rd, float value, ARM64Reg scratch) {
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void ARM64FloatEmitter::MOVI2FDUP(ARM64Reg Rd, float value, ARM64Reg scratch, bool negate) {
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_assert_msg_(!IsSingle(Rd), "%s doesn't support singles", __FUNCTION__);
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// TODO: Make it work with more element sizes
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// TODO: Optimize - there are shorter solution for many values
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ARM64Reg s = (ARM64Reg)(S0 + DecodeReg(Rd));
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int ival;
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memcpy(&ival, &value, 4);
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uint8_t imm8;
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if (ival == 0) { // Make sure to not catch negative zero here
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EOR(Rd, Rd, Rd);
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// Prefer MOVI 0, which may have no latency on some CPUs.
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MOVI(32, Rd, 0);
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if (negate)
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FNEG(32, Rd, Rd);
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} else if (negate && FPImm8FromFloat(-value, &imm8)) {
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FMOV(32, Rd, imm8);
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} else if (FPImm8FromFloat(value, &imm8)) {
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FMOV(32, Rd, imm8);
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if (negate) {
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FNEG(32, Rd, Rd);
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}
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} else {
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MOVI2F(s, value, scratch);
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DUP(32, Rd, Rd, 0);
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_assert_msg_(scratch != INVALID_REG, "Failed to find a way to generate FP immediate %f without scratch", value);
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if (negate) {
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ival ^= 0x80000000;
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}
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m_emit->MOVI2R(scratch, ival);
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DUP(32, Rd, scratch);
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}
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}
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@ -820,6 +820,13 @@ public:
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void FSQRT(ARM64Reg Rd, ARM64Reg Rn);
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void FMOV(ARM64Reg Rd, ARM64Reg Rn, bool top = false); // Also generalized move between GPR/FP
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// Scalar - pairwise
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void FADDP(ARM64Reg Rd, ARM64Reg Rn);
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void FMAXP(ARM64Reg Rd, ARM64Reg Rn);
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void FMINP(ARM64Reg Rd, ARM64Reg Rn);
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void FMAXNMP(ARM64Reg Rd, ARM64Reg Rn);
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void FMINNMP(ARM64Reg Rd, ARM64Reg Rn);
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// Scalar - 2 Source
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void FADD(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void FMUL(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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@ -847,6 +854,7 @@ public:
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void DUP(u8 size, ARM64Reg Rd, ARM64Reg Rn, u8 index);
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void FABS(u8 size, ARM64Reg Rd, ARM64Reg Rn);
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void FADD(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void FADDP(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void FMAX(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void FMLA(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void FMLS(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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@ -893,6 +901,14 @@ public:
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void UMOV(u8 size, ARM64Reg Rd, ARM64Reg Rn, u8 index);
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void SMOV(u8 size, ARM64Reg Rd, ARM64Reg Rn, u8 index);
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// Vector immediates
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void FMOV(u8 size, ARM64Reg Rd, u8 imm8);
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// MSL means bits shifted in are 1s. For size=64, each bit of imm8 is expanded to 8 actual bits.
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void MOVI(u8 size, ARM64Reg Rd, u8 imm8, u8 shift = 0, bool MSL = false);
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void MVNI(u8 size, ARM64Reg Rd, u8 imm8, u8 shift = 0, bool MSL = false);
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void ORR(u8 size, ARM64Reg Rd, u8 imm8, u8 shift = 0);
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void BIC(u8 size, ARM64Reg Rd, u8 imm8, u8 shift = 0);
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// One source
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void FCVT(u8 size_to, u8 size_from, ARM64Reg Rd, ARM64Reg Rn);
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@ -958,7 +974,7 @@ public:
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void FMLA(u8 esize, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, u8 index);
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void MOVI2F(ARM64Reg Rd, float value, ARM64Reg scratch = INVALID_REG, bool negate = false);
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void MOVI2FDUP(ARM64Reg Rd, float value, ARM64Reg scratch = INVALID_REG);
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void MOVI2FDUP(ARM64Reg Rd, float value, ARM64Reg scratch = INVALID_REG, bool negate = false);
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// ABI related
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void ABI_PushRegisters(uint32_t gpr_registers, uint32_t fp_registers);
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@ -973,6 +989,7 @@ private:
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void EmitScalar2Source(bool M, bool S, u32 type, u32 opcode, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void EmitThreeSame(bool U, u32 size, u32 opcode, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void EmitCopy(bool Q, u32 op, u32 imm5, u32 imm4, ARM64Reg Rd, ARM64Reg Rn);
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void EmitScalarPairwise(bool U, u32 size, u32 opcode, ARM64Reg Rd, ARM64Reg Rn);
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void Emit2RegMisc(bool Q, bool U, u32 size, u32 opcode, ARM64Reg Rd, ARM64Reg Rn);
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void EmitLoadStoreSingleStructure(bool L, bool R, u32 opcode, bool S, u32 size, ARM64Reg Rt, ARM64Reg Rn);
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void EmitLoadStoreSingleStructure(bool L, bool R, u32 opcode, bool S, u32 size, ARM64Reg Rt, ARM64Reg Rn, ARM64Reg Rm);
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@ -994,6 +1011,7 @@ private:
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void EmitScalar3Source(bool isDouble, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ARM64Reg Ra, int opcode);
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void EncodeLoadStorePair(u32 size, bool load, IndexType type, ARM64Reg Rt, ARM64Reg Rt2, ARM64Reg Rn, s32 imm);
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void EncodeLoadStoreRegisterOffset(u32 size, bool load, ARM64Reg Rt, ARM64Reg Rn, ArithOption Rm);
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void EncodeModImm(bool Q, u8 op, u8 cmode, u8 o2, ARM64Reg Rd, u8 abcdefgh);
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void SSHLL(u8 src_size, ARM64Reg Rd, ARM64Reg Rn, u32 shift, bool upper);
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void USHLL(u8 src_size, ARM64Reg Rd, ARM64Reg Rn, u32 shift, bool upper);
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@ -40,6 +40,10 @@ namespace MIPSComp {
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using namespace Arm64Gen;
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using namespace Arm64IRJitConstants;
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static bool Overlap(IRReg r1, int l1, IRReg r2, int l2) {
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return r1 < r2 + l2 && r1 + l1 > r2;
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}
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void Arm64JitBackend::CompIR_VecArith(IRInst inst) {
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CONDITIONAL_DISABLE;
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@ -65,7 +69,17 @@ void Arm64JitBackend::CompIR_VecArith(IRInst inst) {
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break;
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case IROp::Vec4Scale:
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CompIR_Generic(inst);
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if (Overlap(inst.dest, 4, inst.src2, 1) || Overlap(inst.src1, 4, inst.src2, 1)) {
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// ARM64 can handle this, but we have to map specially.
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regs_.SpillLockFPR(inst.dest, inst.src1);
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regs_.MapVec4(inst.src1);
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regs_.MapVec4(inst.src2 & ~3);
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regs_.MapVec4(inst.dest, MIPSMap::NOINIT);
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fp_.FMUL(32, regs_.FQ(inst.dest), regs_.FQ(inst.src1), regs_.FQ(inst.src2 & ~3), inst.src2 & 3);
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} else {
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regs_.Map(inst);
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fp_.FMUL(32, regs_.FQ(inst.dest), regs_.FQ(inst.src1), regs_.FQ(inst.src2), 0);
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}
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break;
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case IROp::Vec4Neg:
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@ -370,7 +384,30 @@ void Arm64JitBackend::CompIR_VecAssign(IRInst inst) {
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switch (inst.op) {
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case IROp::Vec4Init:
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CompIR_Generic(inst);
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regs_.Map(inst);
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switch (Vec4Init(inst.src1)) {
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case Vec4Init::AllZERO:
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fp_.MOVI(32, regs_.FQ(inst.dest), 0);
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break;
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case Vec4Init::AllONE:
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case Vec4Init::AllMinusONE:
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fp_.MOVI2FDUP(regs_.FQ(inst.dest), 1.0f, INVALID_REG, Vec4Init(inst.src1) == Vec4Init::AllMinusONE);
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break;
|
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|
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case Vec4Init::Set_1000:
|
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case Vec4Init::Set_0100:
|
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case Vec4Init::Set_0010:
|
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case Vec4Init::Set_0001:
|
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fp_.MOVI(32, regs_.FQ(inst.dest), 0);
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fp_.MOVI2FDUP(EncodeRegToQuad(SCRATCHF1), 1.0f);
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fp_.INS(32, regs_.FQ(inst.dest), inst.src1 - (int)Vec4Init::Set_1000, EncodeRegToQuad(SCRATCHF1), inst.src1 - (int)Vec4Init::Set_1000);
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break;
|
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|
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default:
|
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_assert_msg_(false, "Unexpected Vec4Init value %d", inst.src1);
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DISABLE;
|
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}
|
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break;
|
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|
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case IROp::Vec4Shuffle:
|
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@ -392,7 +429,138 @@ void Arm64JitBackend::CompIR_VecAssign(IRInst inst) {
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break;
|
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|
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case IROp::Vec4Blend:
|
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CompIR_Generic(inst);
|
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regs_.Map(inst);
|
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if (inst.src1 == inst.src2) {
|
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// Shouldn't really happen, just making sure the below doesn't have to think about it.
|
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if (inst.dest != inst.src1)
|
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fp_.MOV(regs_.FQ(inst.dest), regs_.FQ(inst.src1));
|
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break;
|
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}
|
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|
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// To reduce overlap cases to consider, let's inverse src1/src2 if dest == src2.
|
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// Thus, dest could be src1, but no other overlap is possible.
|
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if (inst.dest == inst.src2) {
|
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std::swap(inst.src1, inst.src2);
|
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inst.constant ^= 0xF;
|
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}
|
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|
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switch (inst.constant & 0xF) {
|
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case 0b0000:
|
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if (inst.dest != inst.src1)
|
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fp_.MOV(regs_.FQ(inst.dest), regs_.FQ(inst.src1));
|
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break;
|
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|
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case 0b0001:
|
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if (inst.dest != inst.src1)
|
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fp_.MOV(regs_.FQ(inst.dest), regs_.FQ(inst.src1));
|
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fp_.INS(32, regs_.FQ(inst.dest), 0, regs_.FQ(inst.src2), 0);
|
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break;
|
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case 0b0010:
|
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if (inst.dest != inst.src1)
|
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fp_.MOV(regs_.FQ(inst.dest), regs_.FQ(inst.src1));
|
||||
fp_.INS(32, regs_.FQ(inst.dest), 1, regs_.FQ(inst.src2), 1);
|
||||
break;
|
||||
|
||||
case 0b0011:
|
||||
if (inst.dest != inst.src1)
|
||||
fp_.MOV(regs_.FQ(inst.dest), regs_.FQ(inst.src1));
|
||||
fp_.INS(64, regs_.FQ(inst.dest), 0, regs_.FQ(inst.src2), 0);
|
||||
break;
|
||||
|
||||
case 0b0100:
|
||||
if (inst.dest != inst.src1)
|
||||
fp_.MOV(regs_.FQ(inst.dest), regs_.FQ(inst.src1));
|
||||
fp_.INS(32, regs_.FQ(inst.dest), 2, regs_.FQ(inst.src2), 2);
|
||||
break;
|
||||
|
||||
case 0b0101:
|
||||
// To get AbCd: REV64 to BADC, then TRN2 xAxC, xbxd.
|
||||
fp_.REV64(32, EncodeRegToQuad(SCRATCHF1), regs_.FQ(inst.src2));
|
||||
fp_.TRN2(32, regs_.FQ(inst.dest), EncodeRegToQuad(SCRATCHF1), regs_.FQ(inst.src1));
|
||||
break;
|
||||
|
||||
case 0b0110:
|
||||
if (inst.dest != inst.src1)
|
||||
fp_.MOV(regs_.FQ(inst.dest), regs_.FQ(inst.src1));
|
||||
fp_.INS(32, regs_.FQ(inst.dest), 1, regs_.FQ(inst.src2), 1);
|
||||
fp_.INS(32, regs_.FQ(inst.dest), 2, regs_.FQ(inst.src2), 2);
|
||||
break;
|
||||
|
||||
case 0b0111:
|
||||
if (inst.dest != inst.src1) {
|
||||
fp_.MOV(regs_.FQ(inst.dest), regs_.FQ(inst.src2));
|
||||
fp_.INS(32, regs_.FQ(inst.dest), 3, regs_.FQ(inst.src1), 3);
|
||||
} else {
|
||||
fp_.MOV(EncodeRegToQuad(SCRATCHF1), regs_.FQ(inst.src1));
|
||||
fp_.MOV(regs_.FQ(inst.dest), regs_.FQ(inst.src2));
|
||||
fp_.INS(32, regs_.FQ(inst.dest), 3, EncodeRegToQuad(SCRATCHF1), 3);
|
||||
}
|
||||
break;
|
||||
|
||||
case 0b1000:
|
||||
if (inst.dest != inst.src1)
|
||||
fp_.MOV(regs_.FQ(inst.dest), regs_.FQ(inst.src1));
|
||||
fp_.INS(32, regs_.FQ(inst.dest), 3, regs_.FQ(inst.src2), 3);
|
||||
break;
|
||||
|
||||
case 0b1001:
|
||||
if (inst.dest != inst.src1)
|
||||
fp_.MOV(regs_.FQ(inst.dest), regs_.FQ(inst.src1));
|
||||
fp_.INS(32, regs_.FQ(inst.dest), 0, regs_.FQ(inst.src2), 0);
|
||||
fp_.INS(32, regs_.FQ(inst.dest), 3, regs_.FQ(inst.src2), 3);
|
||||
break;
|
||||
|
||||
case 0b1010:
|
||||
// To get aBcD: REV64 to badc, then TRN2 xaxc, xBxD.
|
||||
fp_.REV64(32, regs_.FQ(inst.dest), regs_.FQ(inst.src1));
|
||||
fp_.TRN2(32, regs_.FQ(inst.dest), regs_.FQ(inst.dest), regs_.FQ(inst.src2));
|
||||
break;
|
||||
|
||||
case 0b1011:
|
||||
if (inst.dest != inst.src1) {
|
||||
fp_.MOV(regs_.FQ(inst.dest), regs_.FQ(inst.src2));
|
||||
fp_.INS(32, regs_.FQ(inst.dest), 2, regs_.FQ(inst.src1), 2);
|
||||
} else {
|
||||
fp_.MOV(EncodeRegToQuad(SCRATCHF1), regs_.FQ(inst.src1));
|
||||
fp_.MOV(regs_.FQ(inst.dest), regs_.FQ(inst.src2));
|
||||
fp_.INS(32, regs_.FQ(inst.dest), 2, EncodeRegToQuad(SCRATCHF1), 2);
|
||||
}
|
||||
break;
|
||||
|
||||
case 0b1100:
|
||||
if (inst.dest != inst.src1)
|
||||
fp_.MOV(regs_.FQ(inst.dest), regs_.FQ(inst.src1));
|
||||
fp_.INS(64, regs_.FQ(inst.dest), 1, regs_.FQ(inst.src2), 1);
|
||||
break;
|
||||
|
||||
case 0b1101:
|
||||
if (inst.dest != inst.src1) {
|
||||
fp_.MOV(regs_.FQ(inst.dest), regs_.FQ(inst.src2));
|
||||
fp_.INS(32, regs_.FQ(inst.dest), 1, regs_.FQ(inst.src1), 1);
|
||||
} else {
|
||||
fp_.MOV(EncodeRegToQuad(SCRATCHF1), regs_.FQ(inst.src1));
|
||||
fp_.MOV(regs_.FQ(inst.dest), regs_.FQ(inst.src2));
|
||||
fp_.INS(32, regs_.FQ(inst.dest), 1, EncodeRegToQuad(SCRATCHF1), 1);
|
||||
}
|
||||
break;
|
||||
|
||||
case 0b1110:
|
||||
if (inst.dest != inst.src1) {
|
||||
fp_.MOV(regs_.FQ(inst.dest), regs_.FQ(inst.src2));
|
||||
fp_.INS(32, regs_.FQ(inst.dest), 0, regs_.FQ(inst.src1), 0);
|
||||
} else {
|
||||
fp_.MOV(EncodeRegToQuad(SCRATCHF1), regs_.FQ(inst.src1));
|
||||
fp_.MOV(regs_.FQ(inst.dest), regs_.FQ(inst.src2));
|
||||
fp_.INS(32, regs_.FQ(inst.dest), 0, EncodeRegToQuad(SCRATCHF1), 0);
|
||||
}
|
||||
break;
|
||||
|
||||
case 0b1111:
|
||||
if (inst.dest != inst.src2)
|
||||
fp_.MOV(regs_.FQ(inst.dest), regs_.FQ(inst.src2));
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case IROp::Vec4Mov:
|
||||
@ -428,7 +596,22 @@ void Arm64JitBackend::CompIR_VecHoriz(IRInst inst) {
|
||||
|
||||
switch (inst.op) {
|
||||
case IROp::Vec4Dot:
|
||||
CompIR_Generic(inst);
|
||||
if (Overlap(inst.dest, 1, inst.src1, 4) || Overlap(inst.dest, 1, inst.src2, 4)) {
|
||||
// To avoid overlap problems, map a little carefully.
|
||||
regs_.SpillLockFPR(inst.src1, inst.src2);
|
||||
regs_.MapVec4(inst.src1);
|
||||
regs_.MapVec4(inst.src2);
|
||||
// It must overlap, so inst.dest is already mapped.
|
||||
fp_.FMUL(32, EncodeRegToQuad(SCRATCHF1), regs_.FQ(inst.src1), regs_.FQ(inst.src2));
|
||||
fp_.FADDP(32, EncodeRegToQuad(SCRATCHF1), EncodeRegToQuad(SCRATCHF1), EncodeRegToQuad(SCRATCHF1));
|
||||
fp_.FADDP(32, EncodeRegToQuad(SCRATCHF1), EncodeRegToQuad(SCRATCHF1), EncodeRegToQuad(SCRATCHF1));
|
||||
fp_.INS(32, regs_.FQ(inst.dest & ~3), inst.dest & 3, EncodeRegToQuad(SCRATCHF1), 0);
|
||||
} else {
|
||||
regs_.Map(inst);
|
||||
fp_.FMUL(32, regs_.FQ(inst.dest), regs_.FQ(inst.src1), regs_.FQ(inst.src2));
|
||||
fp_.FADDP(32, regs_.FQ(inst.dest), regs_.FQ(inst.dest), regs_.FQ(inst.dest));
|
||||
fp_.FADDP(32, regs_.FQ(inst.dest), regs_.FQ(inst.dest), regs_.FQ(inst.dest));
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
|
||||
@ -174,14 +174,18 @@ void RiscVJitBackend::CompIR_VecAssign(IRInst inst) {
|
||||
regs_.Map(inst);
|
||||
for (int i = 0; i < 4; ++i) {
|
||||
int which = (inst.constant >> i) & 1;
|
||||
FMV(32, regs_.F(inst.dest + i), regs_.F((which ? inst.src2 : inst.src1) + i));
|
||||
IRReg srcReg = which ? inst.src2 : inst.src1;
|
||||
if (inst.dest != srcReg)
|
||||
FMV(32, regs_.F(inst.dest + i), regs_.F(srcReg + i));
|
||||
}
|
||||
break;
|
||||
|
||||
case IROp::Vec4Mov:
|
||||
regs_.Map(inst);
|
||||
for (int i = 0; i < 4; ++i)
|
||||
FMV(32, regs_.F(inst.dest + i), regs_.F(inst.src1 + i));
|
||||
if (inst.dest != inst.src1) {
|
||||
regs_.Map(inst);
|
||||
for (int i = 0; i < 4; ++i)
|
||||
FMV(32, regs_.F(inst.dest + i), regs_.F(inst.src1 + i));
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user