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riscv: Add vector int add/sub and many encodings.
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@ -153,7 +153,15 @@ enum class Funct3 {
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CSRRSI = 0b110,
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CSRRCI = 0b111,
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VSETVL = 0b111,
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OPIVV = 0b000,
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OPFVV = 0b001,
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OPMVV = 0b010,
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OPIVI = 0b011,
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OPIVX = 0b100,
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OPFVF = 0b101,
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OPMVX = 0b110,
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OPCFG = 0b111,
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VLS_8 = 0b000,
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VLS_16 = 0b101,
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VLS_32 = 0b110,
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@ -245,6 +253,13 @@ enum class Funct5 {
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FCVT_FROMX = 0b11010,
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FMV_TOX = 0b11100,
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FMV_FROMX = 0b11110,
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VZEXT_VF8 = 0b00010,
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VSEXT_VF8 = 0b00011,
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VZEXT_VF4 = 0b00100,
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VSEXT_VF4 = 0b00101,
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VZEXT_VF2 = 0b00110,
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VSEXT_VF2 = 0b00111,
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};
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enum class Funct4 {
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@ -257,6 +272,144 @@ enum class Funct4 {
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enum class Funct6 {
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C_OP = 0b100011,
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C_OP_32 = 0b100111,
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VADD = 0b000000,
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VSUB = 0b000010,
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VRSUB = 0b000011,
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VMINU = 0b000100,
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VMIN = 0b000101,
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VMAXU = 0b000110,
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VMAX = 0b000111,
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VAND = 0b001001,
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VOR = 0b001010,
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VXOR = 0b001011,
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VRGATHER = 0b001100,
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VSLIDEUP = 0b001110,
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VRGATHEREI16 = 0b001110,
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VSLIDEDOWN = 0b001111,
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VREDSUM = 0b000000,
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VREDAND = 0b000001,
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VREDOR = 0b000010,
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VREDXOR = 0b000011,
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VAADDU = 0b001000,
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VAADD = 0b001001,
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VASUBU = 0b001010,
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VASUB = 0b001011,
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VFREDUSUM = 0b000001,
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VFREDOSUM = 0b000011,
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VFSGNJ = 0b001000,
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VFSGNJN = 0b001001,
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VFSGNJX = 0b001010,
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VADC = 0b010000,
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VMADC = 0b010001,
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VSBC = 0b010010,
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VMSBC = 0b010011,
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VMV = 0b010111,
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VMSEQ = 0b011000,
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VMSNE = 0b011001,
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VMSLTU = 0b011010,
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VMSLT = 0b011011,
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VMSLEU = 0b011100,
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VMSLE = 0b011101,
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VMSGTU = 0b011110,
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VMSGT = 0b011111,
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VMFEQ = 0b011000,
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VMFLE = 0b011001,
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VMFLT = 0b011011,
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VMFNE = 0b011100,
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VMFGT = 0b011101,
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VMFGE = 0b011111,
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VRWUNARY0 = 0b010000,
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VFXUNARY0 = 0b010010,
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VFXUNARY1 = 0b010011,
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VMXUNARY0 = 0b010100,
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VCOMPRESS = 0b010111,
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VMANDNOT = 0b011000,
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VMAND = 0b011001,
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VMOR = 0b011010,
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VMXOR = 0b011011,
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VMORNOT = 0b011100,
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VMNAND = 0b011101,
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VMNOR = 0b011110,
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VMXNOR = 0b011111,
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VSADDU = 0b100000,
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VSADD = 0b100001,
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VSSUBU = 0b100010,
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VSSUB = 0b100011,
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VSLL = 0b100101,
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VSMUL = 0b100111,
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VSRL = 0b101000,
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VSRA = 0b101001,
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VSSRL = 0b101010,
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VSSRA = 0b101011,
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VNSRL = 0b101100,
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VNSRA = 0b101101,
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VNCLIPU = 0b101110,
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VNCLIP = 0b101111,
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VDIVU = 0b100000,
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VDIV = 0b100001,
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VREMU = 0b100010,
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VREM = 0b100011,
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VMULHU = 0b100100,
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VMUL = 0b100101,
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VMULHSU = 0b100110,
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VMULH = 0b100111,
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VMADD = 0b101001,
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VMMSUB = 0b101011,
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VMACC = 0b101101,
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VMMSAC = 0b101111,
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VFDIV = 0b100000,
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VFRDIV = 0b100001,
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VFMUL = 0b100100,
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VFRSUB = 0b100111,
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VFMADD = 0b101000,
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VFNMADD = 0b101001,
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VFMSUB = 0b101010,
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VFNMSUB = 0b101011,
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VFMACC = 0b101100,
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VFNMACC = 0b101101,
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VFMSAC = 0b101110,
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VFNMSAC = 0b101111,
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VWREDSUMU = 0b110000,
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VWREDSUM = 0b110001,
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VWADDU = 0b110000,
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VWADD = 0b110001,
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VWSUBU = 0b110010,
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VWSUB = 0b110011,
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VWADDU_W = 0b110100,
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VWADD_W = 0b110101,
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VWSUBU_W = 0b110110,
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VWSUB_W = 0b110111,
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VWMULU = 0b111000,
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VWMULSU = 0b111010,
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VWMUL = 0b111011,
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VWMACCU = 0b111100,
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VWMACC = 0b111101,
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VWMACCUS = 0b111110,
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VWMACCSU = 0b111111,
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VFWADD = 0b110000,
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VFWREDUSUM = 0b110001,
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VFWSUB = 0b110010,
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VFWREDOSUM = 0b110011,
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VFWADD_W = 0b110100,
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VFWSUB_W = 0b110110,
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VFWMUL = 0b111000,
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VFWMACC = 0b111100,
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VFWNMACC = 0b111101,
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VFWMSAC = 0b111110,
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VFWNMSAC = 0b111111,
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};
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enum class Funct12 {
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@ -361,9 +514,9 @@ static inline u32 EncodeR(Opcode32 opcode, RiscVReg rd, Funct3 funct3, RiscVReg
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}
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static inline u32 EncodeFR(Opcode32 opcode, RiscVReg rd, Funct3 funct3, RiscVReg rs1, RiscVReg rs2, Funct2 funct2, Funct5 funct5) {
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_assert_msg_(IsFPR(rd), "R4 instruction rd must be FPR");
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_assert_msg_(IsFPR(rs1), "R4 instruction rs1 must be FPR");
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_assert_msg_(IsFPR(rs2), "R4 instruction rs2 must be FPR");
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_assert_msg_(IsFPR(rd), "FR instruction rd must be FPR");
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_assert_msg_(IsFPR(rs1), "FR instruction rs1 must be FPR");
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_assert_msg_(IsFPR(rs2), "FR instruction rs2 must be FPR");
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return EncodeR(opcode, rd, funct3, rs1, rs2, (Funct7)(((u32)funct5 << 2) | (u32)funct2));
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}
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@ -443,6 +596,54 @@ static inline u32 EncodeGJ(Opcode32 opcode, RiscVReg rd, s32 simm21) {
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return EncodeJ(opcode, rd, simm21);
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}
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static inline u32 EncodeV(RiscVReg vd, Funct3 funct3, RiscVReg vs1, RiscVReg vs2, VUseMask vm, Funct6 funct6) {
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_assert_msg_(SupportsVector(), "V instruction not supported");
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_assert_msg_(IsVPR(vs2), "V instruction vs2 must be VPR");
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return EncodeR(Opcode32::OP_V, vd, funct3, vs1, vs2, (Funct7)(((s32)funct6 << 1) | (s32)vm));
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}
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static inline u32 EncodeVV(RiscVReg vd, Funct3 funct3, RiscVReg vs1, RiscVReg vs2, VUseMask vm, Funct6 funct6) {
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_assert_msg_(IsVPR(vd), "VV instruction vd must be VPR");
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_assert_msg_(IsVPR(vs1), "VV instruction vs1 must be VPR");
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return EncodeV(vd, funct3, vs1, vs2, vm, funct6);
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}
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static inline u32 EncodeIVV(RiscVReg vd, RiscVReg vs1, RiscVReg vs2, VUseMask vm, Funct6 funct6) {
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return EncodeVV(vd, Funct3::OPIVV, vs1, vs2, vm, funct6);
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}
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static inline u32 EncodeMVV(RiscVReg vd, RiscVReg vs1, RiscVReg vs2, VUseMask vm, Funct6 funct6) {
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return EncodeVV(vd, Funct3::OPMVV, vs1, vs2, vm, funct6);
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}
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static inline u32 EncodeFVV(RiscVReg vd, RiscVReg vs1, RiscVReg vs2, VUseMask vm, Funct6 funct6) {
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return EncodeVV(vd, Funct3::OPFVV, vs1, vs2, vm, funct6);
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}
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static inline u32 EncodeIVI(RiscVReg vd, s8 simm5, RiscVReg vs2, VUseMask vm, Funct6 funct6) {
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_assert_msg_(IsVPR(vd), "IVI instruction vd must be VPR");
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_assert_msg_(SignReduce32(simm5, 5) == simm5, "VI immediate must be signed 5-bit: %d", simm5);
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return EncodeV(vd, Funct3::OPIVI, (RiscVReg)(simm5 & 0x1F), vs2, vm, funct6);
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}
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static inline u32 EncodeIVX(RiscVReg vd, RiscVReg rs1, RiscVReg vs2, VUseMask vm, Funct6 funct6) {
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_assert_msg_(IsVPR(vd), "IVX instruction vd must be VPR");
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_assert_msg_(IsGPR(rs1), "IVX instruction rs1 must be GPR");
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return EncodeV(vd, Funct3::OPIVX, rs1, vs2, vm, funct6);
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}
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static inline u32 EncodeMVX(RiscVReg vd, RiscVReg rs1, RiscVReg vs2, VUseMask vm, Funct6 funct6) {
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_assert_msg_(IsVPR(vd), "MVX instruction vd must be VPR");
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_assert_msg_(IsGPR(rs1), "MVX instruction rs1 must be GPR");
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return EncodeV(vd, Funct3::OPMVX, rs1, vs2, vm, funct6);
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}
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static inline u32 EncodeFVF(RiscVReg vd, RiscVReg fs1, RiscVReg vs2, VUseMask vm, Funct6 funct6) {
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_assert_msg_(IsVPR(vd), "FVF instruction vd must be VPR");
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_assert_msg_(IsFPR(fs1), "FVF instruction fs1 must be FPR");
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return EncodeV(vd, Funct3::OPFVF, fs1, vs2, vm, funct6);
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}
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static inline u16 EncodeCR(Opcode16 op, RiscVReg rs2, RiscVReg rd, Funct4 funct4) {
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_assert_msg_(SupportsCompressed(), "Compressed instructions unsupported");
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return (u16)op | ((u16)rs2 << 2) | ((u16)rd << 7) | ((u16)funct4 << 12);
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@ -634,6 +835,21 @@ static s32 VecLSToSimm12(VLSUMop lsumop, VUseMask vm, VMop mop, int bits, int nf
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return VecLSToSimm12((RiscVReg)(int)lsumop, vm, mop, bits, nf);
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}
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static Funct5 VExtFracToFunct5(int frac, bool sign) {
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_assert_msg_(SupportsVector(), "v%cext instruction not supported", sign ? 's' : 'z');
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switch (frac) {
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case 8:
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return sign ? Funct5::VSEXT_VF8 : Funct5::VZEXT_VF8;
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case 4:
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return sign ? Funct5::VSEXT_VF4 : Funct5::VZEXT_VF4;
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case 2:
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return sign ? Funct5::VSEXT_VF2 : Funct5::VZEXT_VF2;
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default:
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_assert_msg_(false, "Invalid v%cext frac %d", sign ? 's' : 'z', frac);
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return Funct5::VZEXT_VF8;
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}
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}
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RiscVEmitter::RiscVEmitter(const u8 *ptr, u8 *writePtr) {
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SetCodePointer(ptr, writePtr);
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}
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@ -1824,7 +2040,7 @@ void RiscVEmitter::VSETVLI(RiscVReg rd, RiscVReg rs1, VType vtype) {
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_assert_msg_((vtype.value & ~0xFF) == 0, "%s with invalid vtype", __func__);
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_assert_msg_(IsGPR(rd), "%s rd (VL) must be GPR", __func__);
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_assert_msg_(IsGPR(rs1), "%s rs1 (AVL) must be GPR", __func__);
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Write32(EncodeI(Opcode32::OP_V, rd, Funct3::VSETVL, rs1, (s32)vtype.value));
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Write32(EncodeI(Opcode32::OP_V, rd, Funct3::OPCFG, rs1, (s32)vtype.value));
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}
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void RiscVEmitter::VSETIVLI(RiscVReg rd, u8 uimm5, VType vtype) {
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@ -1833,7 +2049,7 @@ void RiscVEmitter::VSETIVLI(RiscVReg rd, u8 uimm5, VType vtype) {
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_assert_msg_(IsGPR(rd), "%s rd (VL) must be GPR", __func__);
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_assert_msg_((u32)uimm5 <= 0x1F, "%s (AVL) can only set up to 31", __func__);
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s32 simm12 = 0xFFFFFC00 | vtype.value;
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Write32(EncodeI(Opcode32::OP_V, rd, Funct3::VSETVL, (RiscVReg)uimm5, (s32)vtype.value));
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Write32(EncodeI(Opcode32::OP_V, rd, Funct3::OPCFG, (RiscVReg)uimm5, (s32)vtype.value));
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}
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void RiscVEmitter::VSETVL(RiscVReg rd, RiscVReg rs1, RiscVReg rs2) {
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@ -1841,7 +2057,7 @@ void RiscVEmitter::VSETVL(RiscVReg rd, RiscVReg rs1, RiscVReg rs2) {
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_assert_msg_(IsGPR(rd), "%s rd (VL) must be GPR", __func__);
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_assert_msg_(IsGPR(rs1), "%s rs1 (AVL) must be GPR", __func__);
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_assert_msg_(IsGPR(rs2), "%s rs2 (vtype) must be GPR", __func__);
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Write32(EncodeI(Opcode32::OP_V, rd, Funct3::VSETVL, rs1, rs2));
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Write32(EncodeI(Opcode32::OP_V, rd, Funct3::OPCFG, rs1, rs2));
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}
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void RiscVEmitter::VLM_V(RiscVReg vd, RiscVReg rs1) {
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@ -1967,6 +2183,181 @@ void RiscVEmitter::VSR_V(int regs, RiscVReg vs3, RiscVReg rs1) {
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Write32(EncodeI(Opcode32::STORE_FP, vs3, VecBitsToFunct3(8), rs1, simm12));
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}
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void RiscVEmitter::VADD_VV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm) {
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Write32(EncodeIVV(vd, vs1, vs2, vm, Funct6::VADD));
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}
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void RiscVEmitter::VADD_VX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm) {
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Write32(EncodeIVX(vd, rs1, vs2, vm, Funct6::VADD));
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}
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void RiscVEmitter::VADD_VI(RiscVReg vd, RiscVReg vs2, s8 simm5, VUseMask vm) {
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Write32(EncodeIVI(vd, simm5, vs2, vm, Funct6::VADD));
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}
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void RiscVEmitter::VSUB_VV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm) {
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Write32(EncodeIVV(vd, vs1, vs2, vm, Funct6::VSUB));
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}
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void RiscVEmitter::VSUB_VX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm) {
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Write32(EncodeIVX(vd, rs1, vs2, vm, Funct6::VSUB));
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}
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void RiscVEmitter::VRSUB_VX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm) {
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Write32(EncodeIVX(vd, rs1, vs2, vm, Funct6::VRSUB));
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}
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void RiscVEmitter::VRSUB_VI(RiscVReg vd, RiscVReg vs2, s8 simm5, VUseMask vm) {
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if (simm5 == 0) {
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// Normalize, this is the preferred form.
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VRSUB_VX(vd, vs2, X0, vm);
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return;
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}
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Write32(EncodeIVI(vd, simm5, vs2, vm, Funct6::VRSUB));
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}
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void RiscVEmitter::VWADDU_VV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm) {
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Write32(EncodeMVV(vd, vs1, vs2, vm, Funct6::VWADDU));
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}
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void RiscVEmitter::VWADDU_VX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm) {
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Write32(EncodeMVX(vd, rs1, vs2, vm, Funct6::VWADDU));
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}
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void RiscVEmitter::VWSUBU_VV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm) {
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Write32(EncodeMVV(vd, vs1, vs2, vm, Funct6::VWSUBU));
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}
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void RiscVEmitter::VWSUBU_VX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm) {
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Write32(EncodeMVX(vd, rs1, vs2, vm, Funct6::VWSUBU));
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}
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void RiscVEmitter::VWADD_VV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm) {
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Write32(EncodeMVV(vd, vs1, vs2, vm, Funct6::VWADD));
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}
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void RiscVEmitter::VWADD_VX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm) {
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Write32(EncodeMVX(vd, rs1, vs2, vm, Funct6::VWADD));
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}
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void RiscVEmitter::VWSUB_VV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm) {
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Write32(EncodeMVV(vd, vs1, vs2, vm, Funct6::VWSUB));
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}
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void RiscVEmitter::VWSUB_VX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm) {
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Write32(EncodeMVX(vd, rs1, vs2, vm, Funct6::VWSUB));
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}
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void RiscVEmitter::VWADDU_WV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm) {
|
||||
Write32(EncodeMVV(vd, vs1, vs2, vm, Funct6::VWADDU_W));
|
||||
}
|
||||
|
||||
void RiscVEmitter::VWADDU_WX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm) {
|
||||
Write32(EncodeMVX(vd, rs1, vs2, vm, Funct6::VWADDU_W));
|
||||
}
|
||||
|
||||
void RiscVEmitter::VWSUBU_WV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm) {
|
||||
Write32(EncodeMVV(vd, vs1, vs2, vm, Funct6::VWSUBU_W));
|
||||
}
|
||||
|
||||
void RiscVEmitter::VWSUBU_WX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm) {
|
||||
Write32(EncodeMVX(vd, rs1, vs2, vm, Funct6::VWSUBU_W));
|
||||
}
|
||||
|
||||
void RiscVEmitter::VWADD_WV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm) {
|
||||
Write32(EncodeMVV(vd, vs1, vs2, vm, Funct6::VWADD_W));
|
||||
}
|
||||
|
||||
void RiscVEmitter::VWADD_WX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm) {
|
||||
Write32(EncodeMVX(vd, rs1, vs2, vm, Funct6::VWADD_W));
|
||||
}
|
||||
|
||||
void RiscVEmitter::VWSUB_WV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm) {
|
||||
Write32(EncodeMVV(vd, vs1, vs2, vm, Funct6::VWSUB_W));
|
||||
}
|
||||
|
||||
void RiscVEmitter::VWSUB_WX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm) {
|
||||
Write32(EncodeMVX(vd, rs1, vs2, vm, Funct6::VWSUB_W));
|
||||
}
|
||||
|
||||
void RiscVEmitter::VZEXT_V(int frac, RiscVReg vd, RiscVReg vs2, VUseMask vm) {
|
||||
Write32(EncodeMVX(vd, (RiscVReg)VExtFracToFunct5(frac, false), vs2, vm, Funct6::VFXUNARY0));
|
||||
}
|
||||
|
||||
void RiscVEmitter::VSEXT_V(int frac, RiscVReg vd, RiscVReg vs2, VUseMask vm) {
|
||||
Write32(EncodeMVX(vd, (RiscVReg)VExtFracToFunct5(frac, true), vs2, vm, Funct6::VFXUNARY0));
|
||||
}
|
||||
|
||||
void RiscVEmitter::VADC_VVM(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, RiscVReg vmask) {
|
||||
_assert_msg_(vmask == V0, "vmask must be V0");
|
||||
Write32(EncodeIVV(vd, vs1, vs2, VUseMask::V0_T, Funct6::VADC));
|
||||
}
|
||||
|
||||
void RiscVEmitter::VADC_VXM(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, RiscVReg vmask) {
|
||||
_assert_msg_(vmask == V0, "vmask must be V0");
|
||||
Write32(EncodeIVX(vd, rs1, vs2, VUseMask::V0_T, Funct6::VADC));
|
||||
}
|
||||
|
||||
void RiscVEmitter::VADC_VIM(RiscVReg vd, RiscVReg vs2, s8 simm5, RiscVReg vmask) {
|
||||
_assert_msg_(vmask == V0, "vmask must be V0");
|
||||
Write32(EncodeIVI(vd, simm5, vs2, VUseMask::V0_T, Funct6::VADC));
|
||||
}
|
||||
|
||||
void RiscVEmitter::VMADC_VVM(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, RiscVReg vmask) {
|
||||
_assert_msg_(vmask == V0, "vmask must be V0");
|
||||
Write32(EncodeIVV(vd, vs1, vs2, VUseMask::V0_T, Funct6::VMADC));
|
||||
}
|
||||
|
||||
void RiscVEmitter::VMADC_VXM(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, RiscVReg vmask) {
|
||||
_assert_msg_(vmask == V0, "vmask must be V0");
|
||||
Write32(EncodeIVX(vd, rs1, vs2, VUseMask::V0_T, Funct6::VMADC));
|
||||
}
|
||||
|
||||
void RiscVEmitter::VMADC_VIM(RiscVReg vd, RiscVReg vs2, s8 simm5, RiscVReg vmask) {
|
||||
_assert_msg_(vmask == V0, "vmask must be V0");
|
||||
Write32(EncodeIVI(vd, simm5, vs2, VUseMask::V0_T, Funct6::VMADC));
|
||||
}
|
||||
|
||||
void RiscVEmitter::VMADC_VV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1) {
|
||||
Write32(EncodeIVV(vd, vs1, vs2, VUseMask::NONE, Funct6::VMADC));
|
||||
}
|
||||
|
||||
void RiscVEmitter::VMADC_VX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1) {
|
||||
Write32(EncodeIVX(vd, rs1, vs2, VUseMask::NONE, Funct6::VMADC));
|
||||
}
|
||||
|
||||
void RiscVEmitter::VMADC_VI(RiscVReg vd, RiscVReg vs2, s8 simm5) {
|
||||
Write32(EncodeIVI(vd, simm5, vs2, VUseMask::NONE, Funct6::VMADC));
|
||||
}
|
||||
|
||||
void RiscVEmitter::VSBC_VVM(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, RiscVReg vmask) {
|
||||
_assert_msg_(vmask == V0, "vmask must be V0");
|
||||
Write32(EncodeIVV(vd, vs1, vs2, VUseMask::V0_T, Funct6::VSBC));
|
||||
}
|
||||
|
||||
void RiscVEmitter::VSBC_VXM(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, RiscVReg vmask) {
|
||||
_assert_msg_(vmask == V0, "vmask must be V0");
|
||||
Write32(EncodeIVX(vd, rs1, vs2, VUseMask::V0_T, Funct6::VSBC));
|
||||
}
|
||||
|
||||
void RiscVEmitter::VMSBC_VVM(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, RiscVReg vmask) {
|
||||
_assert_msg_(vmask == V0, "vmask must be V0");
|
||||
Write32(EncodeIVV(vd, vs1, vs2, VUseMask::V0_T, Funct6::VMSBC));
|
||||
}
|
||||
|
||||
void RiscVEmitter::VMSBC_VXM(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, RiscVReg vmask) {
|
||||
_assert_msg_(vmask == V0, "vmask must be V0");
|
||||
Write32(EncodeIVX(vd, rs1, vs2, VUseMask::V0_T, Funct6::VMSBC));
|
||||
}
|
||||
|
||||
void RiscVEmitter::VMSBC_VV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1) {
|
||||
Write32(EncodeIVV(vd, vs1, vs2, VUseMask::NONE, Funct6::VMSBC));
|
||||
}
|
||||
|
||||
void RiscVEmitter::VMSBC_VX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1) {
|
||||
Write32(EncodeIVX(vd, rs1, vs2, VUseMask::NONE, Funct6::VMSBC));
|
||||
}
|
||||
|
||||
bool RiscVEmitter::AutoCompress() const {
|
||||
return SupportsCompressed() && autoCompress_;
|
||||
}
|
||||
|
||||
@ -470,6 +470,54 @@ public:
|
||||
void VSOXSEGEI_V(int fields, int indexBits, RiscVReg vs3, RiscVReg rs1, RiscVReg vs2, VUseMask vm = VUseMask::NONE);
|
||||
void VSR_V(int regs, RiscVReg vs3, RiscVReg rs1);
|
||||
|
||||
void VADD_VV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm = VUseMask::NONE);
|
||||
void VADD_VX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm = VUseMask::NONE);
|
||||
void VADD_VI(RiscVReg vd, RiscVReg vs2, s8 simm5, VUseMask vm = VUseMask::NONE);
|
||||
void VSUB_VV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm = VUseMask::NONE);
|
||||
void VSUB_VX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm = VUseMask::NONE);
|
||||
void VRSUB_VX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm = VUseMask::NONE);
|
||||
void VRSUB_VI(RiscVReg vd, RiscVReg vs2, s8 simm5, VUseMask vm = VUseMask::NONE);
|
||||
void VNEG_V(RiscVReg vd, RiscVReg vs2, VUseMask vm = VUseMask::NONE) {
|
||||
VRSUB_VX(vd, vs2, X0, vm);
|
||||
}
|
||||
|
||||
void VWADDU_VV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm = VUseMask::NONE);
|
||||
void VWADDU_VX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm = VUseMask::NONE);
|
||||
void VWSUBU_VV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm = VUseMask::NONE);
|
||||
void VWSUBU_VX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm = VUseMask::NONE);
|
||||
void VWADD_VV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm = VUseMask::NONE);
|
||||
void VWADD_VX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm = VUseMask::NONE);
|
||||
void VWSUB_VV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm = VUseMask::NONE);
|
||||
void VWSUB_VX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm = VUseMask::NONE);
|
||||
void VWADDU_WV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm = VUseMask::NONE);
|
||||
void VWADDU_WX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm = VUseMask::NONE);
|
||||
void VWSUBU_WV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm = VUseMask::NONE);
|
||||
void VWSUBU_WX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm = VUseMask::NONE);
|
||||
void VWADD_WV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm = VUseMask::NONE);
|
||||
void VWADD_WX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm = VUseMask::NONE);
|
||||
void VWSUB_WV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm = VUseMask::NONE);
|
||||
void VWSUB_WX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm = VUseMask::NONE);
|
||||
|
||||
void VZEXT_V(int frac, RiscVReg vd, RiscVReg vs2, VUseMask vm = VUseMask::NONE);
|
||||
void VSEXT_V(int frac, RiscVReg vd, RiscVReg vs2, VUseMask vm = VUseMask::NONE);
|
||||
|
||||
// vmask must be V0, provided for clarity/reminder.
|
||||
void VADC_VVM(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, RiscVReg vmask);
|
||||
void VADC_VXM(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, RiscVReg vmask);
|
||||
void VADC_VIM(RiscVReg vd, RiscVReg vs2, s8 simm5, RiscVReg vmask);
|
||||
void VMADC_VVM(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, RiscVReg vmask);
|
||||
void VMADC_VXM(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, RiscVReg vmask);
|
||||
void VMADC_VIM(RiscVReg vd, RiscVReg vs2, s8 simm5, RiscVReg vmask);
|
||||
void VMADC_VV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1);
|
||||
void VMADC_VX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1);
|
||||
void VMADC_VI(RiscVReg vd, RiscVReg vs2, s8 simm5);
|
||||
void VSBC_VVM(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, RiscVReg vmask);
|
||||
void VSBC_VXM(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, RiscVReg vmask);
|
||||
void VMSBC_VVM(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, RiscVReg vmask);
|
||||
void VMSBC_VXM(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, RiscVReg vmask);
|
||||
void VMSBC_VV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1);
|
||||
void VMSBC_VX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1);
|
||||
|
||||
// Compressed instructions.
|
||||
void C_ADDI4SPN(RiscVReg rd, u32 nzuimm10);
|
||||
void C_FLD(RiscVReg rd, RiscVReg addr, u8 uimm8);
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user