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arm64jit: Use reg sum for LDR/STR.

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Skips an add, and should be less ops anyway.
This commit is contained in:
Unknown W. Brackets 2017-12-28 09:35:33 -08:00
parent c948a3df00
commit 6fd17fb026
4 changed files with 14 additions and 35 deletions
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2
Common/Arm64Emitter.cpp
View File

@ -2073,7 +2073,7 @@ void ARM64FloatEmitter::EmitLoadStoreImmediate(u8 size, u32 opc, IndexType type,
}
else
{
_assert_msg_(DYNA_REC, !(imm < -256 || imm > 255), "%s immediate offset must be within range of -256 to 256!", __FUNCTION__);
_assert_msg_(DYNA_REC, !(imm < -256 || imm > 255), "%s immediate offset must be within range of -256 to 255!", __FUNCTION__);
encoded_imm = (imm & 0x1FF) << 2;
if (type == INDEX_POST)
encoded_imm |= 1;

18
Core/MIPS/ARM64/Arm64CompFPU.cpp
View File

@ -103,7 +103,7 @@ void Arm64Jit::Comp_FPULS(MIPSOpcode op)
fpr.MapReg(ft, MAP_NOINIT | MAP_DIRTY);
if (gpr.IsImm(rs)) {
u32 addr = (offset + gpr.GetImm(rs)) & 0x3FFFFFFF;
gpr.SetRegImm(SCRATCH1_64, (uintptr_t)(Memory::base + addr));
gpr.SetRegImm(SCRATCH1, addr);
} else {
gpr.MapReg(rs);
if (g_Config.bFastMemory) {
@ -111,13 +111,8 @@ void Arm64Jit::Comp_FPULS(MIPSOpcode op)
} else {
skips = SetScratch1ForSafeAddress(rs, offset, SCRATCH2);
}
if (jo.enablePointerify) {
MOVK(SCRATCH1_64, ((uint64_t)Memory::base) >> 32, SHIFT_32);
} else {
ADD(SCRATCH1_64, SCRATCH1_64, MEMBASEREG);
}
}
fp.LDR(32, INDEX_UNSIGNED, fpr.R(ft), SCRATCH1_64, 0);
fp.LDR(32, fpr.R(ft), SCRATCH1_64, ArithOption(MEMBASEREG));
for (auto skip : skips) {
SetJumpTarget(skip);
}
@ -135,7 +130,7 @@ void Arm64Jit::Comp_FPULS(MIPSOpcode op)
fpr.MapReg(ft);
if (gpr.IsImm(rs)) {
u32 addr = (offset + gpr.GetImm(rs)) & 0x3FFFFFFF;
gpr.SetRegImm(SCRATCH1_64, addr + (uintptr_t)(Memory::base));
gpr.SetRegImm(SCRATCH1, addr);
} else {
gpr.MapReg(rs);
if (g_Config.bFastMemory) {
@ -143,13 +138,8 @@ void Arm64Jit::Comp_FPULS(MIPSOpcode op)
} else {
skips = SetScratch1ForSafeAddress(rs, offset, SCRATCH2);
}
if (jo.enablePointerify) {
MOVK(SCRATCH1_64, ((uint64_t)Memory::base) >> 32, SHIFT_32);
} else {
ADD(SCRATCH1_64, SCRATCH1_64, MEMBASEREG);
}
}
fp.STR(32, INDEX_UNSIGNED, fpr.R(ft), SCRATCH1_64, 0);
fp.STR(32, fpr.R(ft), SCRATCH1_64, ArithOption(MEMBASEREG));
for (auto skip : skips) {
SetJumpTarget(skip);
}

2
Core/MIPS/ARM64/Arm64CompLoadStore.cpp
View File

@ -135,7 +135,7 @@ namespace MIPSComp {
std::vector<FixupBranch> skips;
if (gpr.IsImm(rs) && Memory::IsValidAddress(iaddr)) {
u32 addr = iaddr;
u32 addr = iaddr & 0x3FFFFFFF;
// Need to initialize since this only loads part of the register.
// But rs no longer matters (even if rs == rt) since we have the address.
gpr.MapReg(rt, load ? MAP_DIRTY : 0);

27
Core/MIPS/ARM64/Arm64CompVFPU.cpp
View File

@ -221,8 +221,8 @@ namespace MIPSComp {
// CC might be set by slow path below, so load regs first.
fpr.MapRegV(vt, MAP_DIRTY | MAP_NOINIT);
if (gpr.IsImm(rs)) {
u32 addr = offset + gpr.GetImm(rs);
gpr.SetRegImm(SCRATCH1_64, addr + (uintptr_t)Memory::base);
u32 addr = (offset + gpr.GetImm(rs)) & 0x3FFFFFFF;
gpr.SetRegImm(SCRATCH1, addr);
} else {
gpr.MapReg(rs);
if (g_Config.bFastMemory) {
@ -230,14 +230,8 @@ namespace MIPSComp {
} else {
skips = SetScratch1ForSafeAddress(rs, offset, SCRATCH2);
}
// Pointerify
if (jo.enablePointerify) {
MOVK(SCRATCH1_64, ((uint64_t)Memory::base) >> 32, SHIFT_32);
} else {
ADD(SCRATCH1_64, SCRATCH1_64, MEMBASEREG);
}
}
fp.LDR(32, INDEX_UNSIGNED, fpr.V(vt), SCRATCH1_64, 0);
fp.LDR(32, fpr.V(vt), SCRATCH1_64, ArithOption(MEMBASEREG));
for (auto skip : skips) {
SetJumpTarget(skip);
}
@ -256,8 +250,8 @@ namespace MIPSComp {
// CC might be set by slow path below, so load regs first.
fpr.MapRegV(vt);
if (gpr.IsImm(rs)) {
u32 addr = offset + gpr.GetImm(rs);
gpr.SetRegImm(SCRATCH1_64, addr + (uintptr_t)Memory::base);
u32 addr = (offset + gpr.GetImm(rs)) & 0x3FFFFFFF;
gpr.SetRegImm(SCRATCH1, addr);
} else {
gpr.MapReg(rs);
if (g_Config.bFastMemory) {
@ -265,13 +259,8 @@ namespace MIPSComp {
} else {
skips = SetScratch1ForSafeAddress(rs, offset, SCRATCH2);
}
if (jo.enablePointerify) {
MOVK(SCRATCH1_64, ((uint64_t)Memory::base) >> 32, SHIFT_32);
} else {
ADD(SCRATCH1_64, SCRATCH1_64, MEMBASEREG);
}
}
fp.STR(32, INDEX_UNSIGNED, fpr.V(vt), SCRATCH1_64, 0);
fp.STR(32, fpr.V(vt), SCRATCH1_64, ArithOption(MEMBASEREG));
for (auto skip : skips) {
SetJumpTarget(skip);
}
@ -302,7 +291,7 @@ namespace MIPSComp {
fpr.MapRegsAndSpillLockV(vregs, V_Quad, MAP_DIRTY | MAP_NOINIT);
if (gpr.IsImm(rs)) {
u32 addr = imm + gpr.GetImm(rs);
u32 addr = (imm + gpr.GetImm(rs)) & 0x3FFFFFFF;
gpr.SetRegImm(SCRATCH1_64, addr + (uintptr_t)Memory::base);
} else {
gpr.MapReg(rs);
@ -335,7 +324,7 @@ namespace MIPSComp {
fpr.MapRegsAndSpillLockV(vregs, V_Quad, 0);
if (gpr.IsImm(rs)) {
u32 addr = imm + gpr.GetImm(rs);
u32 addr = (imm + gpr.GetImm(rs)) & 0x3FFFFFFF;
gpr.SetRegImm(SCRATCH1_64, addr + (uintptr_t)Memory::base);
} else {
gpr.MapReg(rs);