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SoftGPU: Jit 16 bit texel decode.
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@ -1075,7 +1075,6 @@ static const float MEMORY_ALIGNED16(byColor565[4]) = { 255.0f / 31.0f, 255.0f /
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void VertexDecoderJitCache::Jit_Color565Morph() {
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MOV(PTRBITS, R(tempReg1), ImmPtr(&gstate_c.morphWeights[0]));
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MOV(32, R(tempReg2), Imm32(1));
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MOVDQA(XMM5, M(color565Mask));
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MOVAPS(XMM6, M(byColor565));
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@ -50,6 +50,11 @@ static const X64Reg bufwReg = RCX;
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static const X64Reg levelReg = R8;
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#endif
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static const X64Reg fpScratchReg1 = XMM1;
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static const X64Reg fpScratchReg2 = XMM2;
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static const X64Reg fpScratchReg3 = XMM3;
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static const X64Reg fpScratchReg4 = XMM4;
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NearestFunc SamplerJitCache::Compile(const SamplerID &id) {
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BeginWrite();
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const u8 *start = this->AlignCode16();
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@ -145,6 +150,7 @@ bool SamplerJitCache::Jit_ReadTextureFormat(const SamplerID &id) {
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success = Jit_ReadClutColor(id);
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break;
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// TODO: DXT?
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default:
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success = false;
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}
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@ -287,15 +293,86 @@ bool SamplerJitCache::Jit_GetTexDataSwizzled(const SamplerID &id, int bitsPerTex
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}
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bool SamplerJitCache::Jit_Decode5650() {
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return false;
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MOV(32, R(tempReg2), R(resultReg));
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AND(32, R(tempReg2), Imm32(0x0000001F));
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// B (we do R and B at the same time, they're both 5.)
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MOV(32, R(tempReg1), R(resultReg));
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AND(32, R(tempReg1), Imm32(0x0000F800));
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SHL(32, R(tempReg1), Imm8(5));
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OR(32, R(tempReg2), R(tempReg1));
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// Expand 5 -> 8. At this point we have 00BB00RR.
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MOV(32, R(tempReg1), R(tempReg2));
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SHL(32, R(tempReg2), Imm8(3));
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SHR(32, R(tempReg1), Imm8(2));
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OR(32, R(tempReg2), R(tempReg1));
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AND(32, R(tempReg2), Imm32(0x00FF00FF));
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// Now's as good a time to put in A as any.
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OR(32, R(tempReg2), Imm32(0xFF000000));
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// Last, we need to align, extract, and expand G.
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// 3 to align to G, and then 2 to expand to 8.
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SHL(32, R(resultReg), Imm8(3 + 2));
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AND(32, R(resultReg), Imm32(0x0000FC00));
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MOV(32, R(tempReg1), R(resultReg));
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// 2 to account for resultReg being preshifted, 4 for expansion.
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SHR(32, R(tempReg1), Imm8(2 + 4));
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OR(32, R(resultReg), R(tempReg1));
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AND(32, R(resultReg), Imm32(0x0000FF00));
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OR(32, R(resultReg), R(tempReg2));;
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return true;
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}
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bool SamplerJitCache::Jit_Decode5551() {
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return false;
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MOV(32, R(tempReg2), R(resultReg));
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MOV(32, R(tempReg1), R(resultReg));
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AND(32, R(tempReg2), Imm32(0x0000001F));
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AND(32, R(tempReg1), Imm32(0x000003E0));
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SHL(32, R(tempReg1), Imm8(3));
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OR(32, R(tempReg2), R(tempReg1));
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MOV(32, R(tempReg1), R(resultReg));
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AND(32, R(tempReg1), Imm32(0x00007C00));
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SHL(32, R(tempReg1), Imm8(6));
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OR(32, R(tempReg2), R(tempReg1));
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// Expand 5 -> 8. After this is just A.
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MOV(32, R(tempReg1), R(tempReg2));
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SHL(32, R(tempReg2), Imm8(3));
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SHR(32, R(tempReg1), Imm8(2));
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// Chop off the bits that were shifted out.
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AND(32, R(tempReg1), Imm32(0x00070707));
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OR(32, R(tempReg2), R(tempReg1));
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// For A, we shift it to a single bit, and then subtract and XOR.
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// That's probably the simplest way to expand it...
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SHR(32, R(resultReg), Imm8(15));
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// If it was 0, it's now -1, otherwise it's 0. Easy.
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SUB(32, R(resultReg), Imm8(1));
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XOR(32, R(resultReg), Imm32(0xFF000000));
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AND(32, R(resultReg), Imm32(0xFF000000));
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OR(32, R(resultReg), R(tempReg2));
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return true;
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}
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static const u32 MEMORY_ALIGNED16(color4444mask[4]) = { 0xf00ff00f, 0xf00ff00f, 0xf00ff00f, 0xf00ff00f, };
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bool SamplerJitCache::Jit_Decode4444() {
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return false;
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MOVD_xmm(fpScratchReg1, R(resultReg));
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PUNPCKLBW(fpScratchReg1, R(fpScratchReg1));
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PAND(fpScratchReg1, M(color4444mask));
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MOVSS(fpScratchReg2, R(fpScratchReg1));
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MOVSS(fpScratchReg3, R(fpScratchReg1));
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PSRLW(fpScratchReg2, 4);
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PSLLW(fpScratchReg3, 4);
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POR(fpScratchReg1, R(fpScratchReg2));
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POR(fpScratchReg1, R(fpScratchReg3));
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MOVD_xmm(R(resultReg), fpScratchReg1);
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return true;
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}
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bool SamplerJitCache::Jit_TransformClutIndex(const SamplerID &id, int bitsPerIndex) {
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