mirror of
https://github.com/hrydgard/ppsspp.git
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Try software rounding mode instead. Use conditionals for VFP functions. Note: Round to Zero not working for some reason?
This commit is contained in:
Sacha
parent
fbef590bed
commit
7782be9a3e
@ -801,13 +801,13 @@ void ARMXEmitter::VLDR(ARMReg Dest, ARMReg Base, u16 offset)
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if (single_reg)
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{
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Write32(NO_COND | (0x1B << 23) | ((Dest & 0x1) << 22) | (1 << 20) | (Base << 16) \
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Write32(condition | (0x1B << 23) | ((Dest & 0x1) << 22) | (1 << 20) | (Base << 16) \
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| ((Dest & 0x1E) << 11) | (10 << 8) | (offset >> 2));
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}
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else
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{
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Write32(NO_COND | (0x1B << 23) | ((Dest & 0x10) << 18) | (1 << 20) | (Base << 16) \
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Write32(condition | (0x1B << 23) | ((Dest & 0x10) << 18) | (1 << 20) | (Base << 16) \
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| ((Dest & 0xF) << 12) | (11 << 8) | (offset >> 2));
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}
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}
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@ -828,13 +828,13 @@ void ARMXEmitter::VSTR(ARMReg Src, ARMReg Base, u16 offset)
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if (single_reg)
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{
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Write32(NO_COND | (0x1B << 23) | ((Src & 0x1) << 22) | (Base << 16) \
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Write32(condition | (0x1B << 23) | ((Src & 0x1) << 22) | (Base << 16) \
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| ((Src & 0x1E) << 11) | (10 << 8) | (offset >> 2));
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}
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else
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{
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Write32(NO_COND | (0x1B << 23) | ((Src & 0x10) << 18) | (Base << 16) \
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Write32(condition | (0x1B << 23) | ((Src & 0x10) << 18) | (Base << 16) \
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| ((Src & 0xF) << 12) | (11 << 8) | (offset >> 2));
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}
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}
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@ -848,12 +848,12 @@ void ARMXEmitter::VCMP(ARMReg Vd, ARMReg Vm, bool E)
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if (single_reg)
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{
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Write32(NO_COND | (0x1D << 23) | ((Vd & 0x1) << 22) | (0x34 << 16) | ((Vd & 0x1E) << 11) \
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Write32(condition | (0x1D << 23) | ((Vd & 0x1) << 22) | (0x34 << 16) | ((Vd & 0x1E) << 11) \
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| (E << 7) | (0x29 << 6) | ((Vm & 0x1) << 5) | (Vm >> 1));
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}
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else
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{
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Write32(NO_COND | (0x1D << 23) | ((Vd & 0x10) << 18) | (0x34 << 16) | ((Vd & 0xF) << 12) \
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Write32(condition | (0x1D << 23) | ((Vd & 0x10) << 18) | (0x34 << 16) | ((Vd & 0xF) << 12) \
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| (E << 7) | (0x2C << 6) | ((Vm & 0x10) << 1) | (Vm & 0xF));
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}
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}
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@ -866,24 +866,24 @@ void ARMXEmitter::VCMP(ARMReg Vd, bool E)
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if (single_reg)
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{
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Write32(NO_COND | (0x1D << 23) | ((Vd & 0x1) << 22) | (0x35 << 16) | ((Vd & 0x1E) << 11) \
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Write32(condition | (0x1D << 23) | ((Vd & 0x1) << 22) | (0x35 << 16) | ((Vd & 0x1E) << 11) \
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| (E << 7) | (0x29 << 6));
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}
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else
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{
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Write32(NO_COND | (0x1D << 23) | ((Vd & 0x10) << 18) | (0x35 << 16) | ((Vd & 0xF) << 12) \
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Write32(condition | (0x1D << 23) | ((Vd & 0x10) << 18) | (0x35 << 16) | ((Vd & 0xF) << 12) \
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| (E << 7) | (0x2C << 6));
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}
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}
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void ARMXEmitter::VMRS_APSR() {
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Write32(NO_COND | 0xEF10A10 | (15 << 12));
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Write32(condition | 0xEF10A10 | (15 << 12));
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}
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void ARMXEmitter::VMRS(ARMReg Rt) {
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Write32(NO_COND | (0xEF << 20) | (1 << 16) | (Rt << 12) | 0xA10);
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Write32(condition | (0xEF << 20) | (1 << 16) | (Rt << 12) | 0xA10);
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}
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void ARMXEmitter::VMSR(ARMReg Rt) {
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Write32(NO_COND | (0xEE << 20) | (1 << 16) | (Rt << 12) | 0xA10);
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Write32(condition | (0xEE << 20) | (1 << 16) | (Rt << 12) | 0xA10);
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}
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void ARMXEmitter::VDIV(ARMReg Vd, ARMReg Vn, ARMReg Vm)
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@ -899,13 +899,13 @@ void ARMXEmitter::VDIV(ARMReg Vd, ARMReg Vn, ARMReg Vm)
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if (single_reg)
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{
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Write32(NO_COND | (0x1D << 23) | ((Vd & 0x1) << 22) | ((Vn & 0x1E) << 15) \
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Write32(condition | (0x1D << 23) | ((Vd & 0x1) << 22) | ((Vn & 0x1E) << 15) \
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| ((Vd & 0x1E) << 11) | (0xA << 8) | ((Vn & 0x1) << 7) | ((Vm & 0x1) << 5) \
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| (Vm >> 1));
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}
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else
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{
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Write32(NO_COND | (0x1D << 23) | ((Vd & 0x10) << 18) | ((Vn & 0xF) << 16) \
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Write32(condition | (0x1D << 23) | ((Vd & 0x10) << 18) | ((Vn & 0xF) << 16) \
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| ((Vd & 0xF) << 12) | (0xB << 8) | ((Vn & 0x10) << 3) | ((Vm & 0x10) << 2) \
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| (Vm & 0xF));
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}
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@ -921,12 +921,12 @@ void ARMXEmitter::VSQRT(ARMReg Vd, ARMReg Vm)
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if (single_reg)
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{
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Write32(NO_COND | (0x1D << 23) | ((Vd & 0x1) << 22) | (0x31 << 16) \
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Write32(condition | (0x1D << 23) | ((Vd & 0x1) << 22) | (0x31 << 16) \
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| ((Vd & 0x1E) << 11) | (0x2B << 6) | ((Vm & 0x1) << 5) | (Vm >> 1));
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}
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else
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{
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Write32(NO_COND | (0x1D << 23) | ((Vd & 0x10) << 18) | (0x31 << 16) \
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Write32(condition | (0x1D << 23) | ((Vd & 0x10) << 18) | (0x31 << 16) \
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| ((Vd & 0xF) << 12) | (0x2F << 6) | ((Vm & 0x10) << 2) | (Vm & 0xF));
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}
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}
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@ -946,7 +946,7 @@ void ARMXEmitter::VADD(ARMReg Vd, ARMReg Vn, ARMReg Vm)
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if (single_reg)
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{
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Write32(NO_COND | (0x1C << 23) | ((Vd & 0x1) << 22) | (0x3 << 20) \
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Write32(condition | (0x1C << 23) | ((Vd & 0x1) << 22) | (0x3 << 20) \
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| ((Vn & 0x1E) << 15) | ((Vd & 0x1E) << 11) | (0x5 << 9) \
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| ((Vn & 0x1) << 7) | ((Vm & 0x1) << 5) | (Vm >> 1));
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}
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@ -954,7 +954,7 @@ void ARMXEmitter::VADD(ARMReg Vd, ARMReg Vn, ARMReg Vm)
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{
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if (double_reg)
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{
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Write32(NO_COND | (0x1C << 23) | ((Vd & 0x10) << 18) | (0x3 << 20) \
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Write32(condition | (0x1C << 23) | ((Vd & 0x10) << 18) | (0x3 << 20) \
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| ((Vn & 0xF) << 16) | ((Vd & 0xF) << 12) | (0xB << 8) \
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| ((Vn & 0x10) << 3) | ((Vm & 0x10) << 2) | (Vm & 0xF));
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}
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@ -981,7 +981,7 @@ void ARMXEmitter::VSUB(ARMReg Vd, ARMReg Vn, ARMReg Vm)
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if (single_reg)
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{
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Write32(NO_COND | (0x1C << 23) | ((Vd & 0x1) << 22) | (0x3 << 20) \
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Write32(condition | (0x1C << 23) | ((Vd & 0x1) << 22) | (0x3 << 20) \
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| ((Vn & 0x1E) << 15) | ((Vd & 0x1E) << 11) | (0x5 << 9) \
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| ((Vn & 0x1) << 7) | (1 << 6) | ((Vm & 0x1) << 5) | (Vm >> 1));
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}
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@ -989,7 +989,7 @@ void ARMXEmitter::VSUB(ARMReg Vd, ARMReg Vn, ARMReg Vm)
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{
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if (double_reg)
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{
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Write32(NO_COND | (0x1C << 23) | ((Vd & 0x10) << 18) | (0x3 << 20) \
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Write32(condition | (0x1C << 23) | ((Vd & 0x10) << 18) | (0x3 << 20) \
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| ((Vn & 0xF) << 16) | ((Vd & 0xF) << 12) | (0xB << 8) \
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| ((Vn & 0x10) << 3) | (1 << 6) | ((Vm & 0x10) << 2) | (Vm & 0xF));
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}
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@ -1017,7 +1017,7 @@ void ARMXEmitter::VMUL(ARMReg Vd, ARMReg Vn, ARMReg Vm)
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if (single_reg)
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{
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Write32(NO_COND | (0x1C << 23) | ((Vd & 0x1) << 22) | (0x2 << 20) \
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Write32(condition | (0x1C << 23) | ((Vd & 0x1) << 22) | (0x2 << 20) \
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| ((Vn & 0x1E) << 15) | ((Vd & 0x1E) << 11) | (0x5 << 9) \
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| ((Vn & 0x1) << 7) | ((Vm & 0x1) << 5) | (Vm >> 1));
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}
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@ -1025,7 +1025,7 @@ void ARMXEmitter::VMUL(ARMReg Vd, ARMReg Vn, ARMReg Vm)
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{
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if (double_reg)
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{
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Write32(NO_COND | (0x1C << 23) | ((Vd & 0x10) << 18) | (0x2 << 20) \
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Write32(condition | (0x1C << 23) | ((Vd & 0x10) << 18) | (0x2 << 20) \
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| ((Vn & 0xF) << 16) | ((Vd & 0xF) << 12) | (0xB << 8) \
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| ((Vn & 0x10) << 3) | ((Vm & 0x10) << 2) | (Vm & 0xF));
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}
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@ -1050,7 +1050,7 @@ void ARMXEmitter::VMLA(ARMReg Vd, ARMReg Vn, ARMReg Vm)
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if (single_reg)
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{
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Write32(NO_COND | (0x1C << 23) | ((Vd & 0x1) << 22) | (0x0 << 20) \
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Write32(condition | (0x1C << 23) | ((Vd & 0x1) << 22) | (0x0 << 20) \
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| ((Vn & 0x1E) << 15) | ((Vd & 0x1E) << 11) | (0x5 << 9) \
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| ((Vn & 0x1) << 7) | ((Vm & 0x1) << 5) | (Vm >> 1));
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}
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@ -1069,12 +1069,12 @@ void ARMXEmitter::VABS(ARMReg Vd, ARMReg Vm)
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if (single_reg)
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{
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Write32(NO_COND | (0x1D << 23) | ((Vd & 0x1) << 22) | (0x30 << 16) \
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Write32(condition | (0x1D << 23) | ((Vd & 0x1) << 22) | (0x30 << 16) \
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| ((Vd & 0x1E) << 11) | (0x2B << 6) | ((Vm & 0x1) << 5) | (Vm >> 1));
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}
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else
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{
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Write32(NO_COND | (0x1D << 23) | ((Vd & 0x10) << 18) | (0x30 << 16) \
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Write32(condition | (0x1D << 23) | ((Vd & 0x10) << 18) | (0x30 << 16) \
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| ((Vd & 0xF) << 12) | (0x2F << 6) | ((Vm & 0x10) << 2) | (Vm & 0xF));
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}
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}
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@ -1088,12 +1088,12 @@ void ARMXEmitter::VNEG(ARMReg Vd, ARMReg Vm)
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if (single_reg)
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{
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Write32(NO_COND | (0x1D << 23) | ((Vd & 0x1) << 22) | (0x31 << 16) \
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Write32(condition | (0x1D << 23) | ((Vd & 0x1) << 22) | (0x31 << 16) \
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| ((Vd & 0x1E) << 11) | (0x29 << 6) | ((Vm & 0x1) << 5) | (Vm >> 1));
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}
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else
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{
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Write32(NO_COND | (0x1D << 23) | ((Vd & 0x10) << 18) | (0x31 << 16) \
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Write32(condition | (0x1D << 23) | ((Vd & 0x10) << 18) | (0x31 << 16) \
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| ((Vd & 0xF) << 12) | (0x2D << 6) | ((Vm & 0x10) << 2) | (Vm & 0xF));
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}
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}
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@ -1105,7 +1105,7 @@ void ARMXEmitter::VMOV(ARMReg Dest, ARMReg Src, bool high)
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Dest = SubBase(Dest);
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Write32(NO_COND | (0xE << 24) | (high << 21) | ((Dest & 0xF) << 16) | (Src << 12) \
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Write32(condition | (0xE << 24) | (high << 21) | ((Dest & 0xF) << 16) | (Src << 12) \
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| (11 << 8) | ((Dest & 0x10) << 3) | (1 << 4));
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}
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@ -1119,7 +1119,7 @@ void ARMXEmitter::VMOV(ARMReg Dest, ARMReg Src)
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{
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// Moving to a Neon register FROM ARM Reg
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Dest = (ARMReg)(Dest - S0);
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Write32(NO_COND | (0xE0 << 20) | ((Dest & 0x1E) << 15) | (Src << 12) \
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Write32(condition | (0xE0 << 20) | ((Dest & 0x1E) << 15) | (Src << 12) \
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| (0xA << 8) | ((Dest & 0x1) << 7) | (1 << 4));
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return;
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}
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@ -1139,7 +1139,7 @@ void ARMXEmitter::VMOV(ARMReg Dest, ARMReg Src)
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{
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// Moving to ARM Reg from Neon Register
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Src = (ARMReg)(Src - S0);
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Write32(NO_COND | (0xE1 << 20) | ((Src & 0x1E) << 15) | (Dest << 12) \
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Write32(condition | (0xE1 << 20) | ((Src & 0x1E) << 15) | (Dest << 12) \
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| (0xA << 8) | ((Src & 0x1) << 7) | (1 << 4));
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return;
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}
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@ -1169,7 +1169,7 @@ void ARMXEmitter::VMOV(ARMReg Dest, ARMReg Src)
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if (Single)
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{
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Write32(NO_COND | (0x1D << 23) | ((Dest & 0x1) << 22) | (0x3 << 20) | ((Dest & 0x1E) << 11) \
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Write32(condition | (0x1D << 23) | ((Dest & 0x1) << 22) | (0x3 << 20) | ((Dest & 0x1E) << 11) \
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| (0x5 << 9) | (1 << 6) | ((Src & 0x1) << 5) | ((Src & 0x1E) >> 1));
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}
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else
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@ -1186,7 +1186,7 @@ void ARMXEmitter::VMOV(ARMReg Dest, ARMReg Src)
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}
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else
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{
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Write32(NO_COND | (0x1D << 23) | ((Dest & 0x10) << 18) | (0x3 << 20) | ((Dest & 0xF) << 12) \
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Write32(condition | (0x1D << 23) | ((Dest & 0x10) << 18) | (0x3 << 20) | ((Dest & 0xF) << 12) \
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| (0x2D << 6) | ((Src & 0x10) << 1) | (Src & 0xF));
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}
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}
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@ -1202,10 +1202,10 @@ void ARMXEmitter::VCVT(ARMReg Dest, ARMReg Source, int flags)
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if (single_reg)
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{
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Write32(NO_COND | (0x1D << 23) | ((Dest & 0x1) << 22) | (0x7 << 19) | ((flags & TO_INT) << 18) | (op2 << 16) \
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Write32(condition | (0x1D << 23) | ((Dest & 0x1) << 22) | (0x7 << 19) | ((flags & TO_INT) << 18) | (op2 << 16) \
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| ((Dest & 0x1E) << 11) | (op << 7) | (0x29 << 6) | ((Source & 0x1) << 5) | (Source >> 1));
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} else {
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Write32(NO_COND | (0x1D << 23) | ((Dest & 0x10) << 18) | (0x7 << 19) | ((flags & TO_INT) << 18) | (op2 << 16) \
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Write32(condition | (0x1D << 23) | ((Dest & 0x10) << 18) | (0x7 << 19) | ((flags & TO_INT) << 18) | (op2 << 16) \
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| ((Dest & 0xF) << 12) | (1 << 8) | (op << 7) | (0x29 << 6) | ((Source & 0x10) << 1) | (Source & 0xF));
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}
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}
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@ -222,10 +222,30 @@ void Jit::Comp_FPU2op(u32 op)
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VCVT(fpr.R(fd), fpr.R(fs), TO_FLOAT | IS_SIGNED);
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break;
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case 36: //FsI(fd) = (int) F(fs); break; //cvt.w.s
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DISABLE;
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// Requires correct floating mode set
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fpr.MapDirtyIn(fd, fs);
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VCVT(fpr.R(fd), fpr.R(fs), TO_INT);
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LDR(R0, CTXREG, offsetof(MIPSState, fcr31));
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AND(R0, R0, Operand2(3));
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// MIPS Rounding Mode:
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// 0: Round nearest
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// 1: Round to zero
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// 2: Round up (ceil)
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// 3: Round down (floor)
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CMP(R0, Operand2(2));
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SetCC(CC_GE);
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MOVI2F(S0, 0.5f, R1);
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SetCC(CC_GT);
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VSUB(S0,fpr.R(fs),S0);
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SetCC(CC_EQ);
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VADD(S0,fpr.R(fs),S0);
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SetCC(CC_GE);
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VCVT(fpr.R(fd), S0, TO_INT | IS_SIGNED); /* 2,3 */
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CMP(R0, Operand2(1));
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SetCC(CC_EQ);
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VCVT(fpr.R(fd), fpr.R(fs), TO_INT | IS_SIGNED | ROUND_TO_ZERO); /* 1 */
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SetCC(CC_LT);
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VCVT(fpr.R(fd), fpr.R(fs), TO_INT | IS_SIGNED); /* 0 */
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SetCC(CC_AL);
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break;
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default:
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DISABLE;
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@ -260,7 +280,7 @@ void Jit::Comp_mxc1(u32 op)
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return;
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case 6: //currentMIPS->WriteFCR(fs, R(rt)); break; //ctc1
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// Rounding isn't right.
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// Hardware rounding method.
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/*if (fs == 31)
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{
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fpr.MapReg(rt, 0);
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@ -269,9 +289,9 @@ void Jit::Comp_mxc1(u32 op)
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// 0, 1, 2, 3 <-> 0, 3, 1, 2
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CMP(R0, Operand2(1));
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SetCC(CC_EQ);
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SUB(R0, R0, Operand2(1));
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SetCC(CC_GT);
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ADD(R0, R0, Operand2(2));
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SetCC(CC_GT);
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SUB(R0, R0, Operand2(1));
|
||||
SetCC(CC_AL);
|
||||
|
||||
// Load and Store RM to FPSCR
|
||||
|
||||
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Reference in New Issue
Block a user