Emulator-Archive/ppsspp
1
0
Fork 0
mirror of https://github.com/hrydgard/ppsspp.git synced 2024-11-26 23:10:38 +00:00
Code Issues Actions 2 Packages Projects Releases Wiki Activity

irjit: Correct another PurgeTemps case.

Browse Source 
In this case:
  Mov A, B
  AndConst A, A, 1
  Load32 C, A, 0

Was still swapping the Load32 to B, not just the AndConst.

Fixes #15735.
This commit is contained in:
Unknown W. Brackets 2022-07-27 19:38:16 -07:00
parent 5abf1362a2
commit 7b081a61c8
2 changed files with 22 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
Core/MIPS/IR/IRPassSimplify.cpp
View File

@ -857,6 +857,15 @@ bool PurgeTemps(const IRWriter &in, IRWriter &out, const IROptions &opts) {
// We're changing "Mov A, B; Add C, C, A" to "Mov A, B; Add C, C, B" here. // We're changing "Mov A, B; Add C, C, A" to "Mov A, B; Add C, C, B" here.
// srcReg should only be set when it was a Mov. // srcReg should only be set when it was a Mov.
inst = IRReplaceSrcGPR(inst, check.reg, check.srcReg); inst = IRReplaceSrcGPR(inst, check.reg, check.srcReg);
// If the Mov modified the same reg as this instruction, we can't optimize from it anymore.
if (inst.dest == check.reg) {
check.reg = 0;
// We can also optimize it out since we've essentially moved now.
insts[check.index].op = IROp::Mov;
insts[check.index].dest = 0;
insts[check.index].src1 = 0;
}
} else if (!IRMutatesDestGPR(insts[check.index], check.reg) && inst.op == IROp::Mov && i == check.index + 1) { } else if (!IRMutatesDestGPR(insts[check.index], check.reg) && inst.op == IROp::Mov && i == check.index + 1) {
// As long as the previous inst wasn't modifying its dest reg, and this is a Mov, we can swap. // As long as the previous inst wasn't modifying its dest reg, and this is a Mov, we can swap.
// We're changing "Add A, B, C; Mov B, A" to "Add B, B, C; Mov A, B" here. // We're changing "Add A, B, C; Mov B, A" to "Add B, B, C; Mov A, B" here.

13
unittest/TestIRPassSimplify.cpp
View File

@ -92,6 +92,19 @@ static const IRVerification tests[] = {
}, },
{ &PurgeTemps }, { &PurgeTemps },
}, },
{
"Load32LeftPurgeTemps",
{
{ IROp::Mov, { IRTEMP_LR_ADDR }, MIPS_REG_A0 },
{ IROp::AndConst, { IRTEMP_LR_ADDR }, IRTEMP_LR_ADDR, 0, 0xFFFFFFFC },
{ IROp::Load32, { MIPS_REG_V0 }, IRTEMP_LR_ADDR, 0, 0 },
},
{
{ IROp::AndConst, { IRTEMP_LR_ADDR }, MIPS_REG_A0, 0, 0xFFFFFFFC },
{ IROp::Load32, { MIPS_REG_V0 }, IRTEMP_LR_ADDR, 0, 0 },
},
{ &PurgeTemps },
},
{ {
"SwapClobberTemp", "SwapClobberTemp",
{ {