mirror of
https://github.com/hrydgard/ppsspp.git
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Merge x64 emitter from a newer Dolphin version.
This one can generate slightly smaller code by exploiting some EAX-only encoding and various other short forms, and adds support for many newer CPU instructions.
This commit is contained in:
Henrik Rydgård
Henrik Rydgard
parent
3b1476c8ec
commit
7bde976069
@ -49,6 +49,17 @@ void do_cpuid(u32 regs[4], u32 cpuid_leaf) {
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#ifdef _M_SSE
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#include <xmmintrin.h>
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#define _XCR_XFEATURE_ENABLED_MASK 0
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static unsigned long long _xgetbv(unsigned int index)
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{
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unsigned int eax, edx;
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__asm__ __volatile__("xgetbv" : "=a"(eax), "=d"(edx) : "c"(index));
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return ((unsigned long long)edx << 32) | eax;
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}
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#else
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#define _XCR_XFEATURE_ENABLED_MASK 0
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#endif
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#if defined __FreeBSD__
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@ -172,6 +183,38 @@ void CPUInfo::Detect() {
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bFMA = true;
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}
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if ((cpu_id[2] >> 25) & 1) bAES = true;
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if ((cpu_id[3] >> 24) & 1)
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{
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// We can use FXSAVE.
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bFXSR = true;
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}
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// AVX support requires 3 separate checks:
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// - Is the AVX bit set in CPUID?
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// - Is the XSAVE bit set in CPUID?
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// - XGETBV result has the XCR bit set.
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if (((cpu_id[2] >> 28) & 1) && ((cpu_id[2] >> 27) & 1))
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{
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if ((_xgetbv(_XCR_XFEATURE_ENABLED_MASK) & 0x6) == 0x6)
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{
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bAVX = true;
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if ((cpu_id[2] >> 12) & 1)
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bFMA = true;
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}
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}
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if (max_std_fn >= 7)
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{
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do_cpuid(cpu_id, 0x00000007);
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// careful; we can't enable AVX2 unless the XSAVE/XGETBV checks above passed
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if ((cpu_id[1] >> 5) & 1)
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bAVX2 = bAVX;
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if ((cpu_id[1] >> 3) & 1)
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bBMI1 = true;
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if ((cpu_id[1] >> 8) & 1)
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bBMI2 = true;
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}
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}
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if (max_ex_fn >= 0x80000004) {
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// Extract brand string
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@ -56,10 +56,15 @@ struct CPUInfo {
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bool bLZCNT;
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bool bSSE4A;
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bool bAVX;
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bool bAVX2;
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bool bFMA;
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bool bAES;
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bool bLAHFSAHF64;
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bool bLongMode;
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bool bBMI1;
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bool bBMI2;
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bool bMOVBE;
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bool bFXSR;
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// ARM specific CPUInfo
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bool bSwp;
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File diff suppressed because it is too large
Load Diff
@ -22,6 +22,10 @@
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#include "Common.h"
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#ifdef _M_X64
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#define _ARCH_64
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#endif
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namespace Gen
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{
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@ -121,6 +125,16 @@ enum {
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CMP_ORD = 7,
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};
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enum FloatOp {
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floatLD = 0,
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floatST = 2,
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floatSTP = 3,
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floatLD80 = 5,
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floatSTP80 = 7,
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floatINVALID = -1,
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};
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class XEmitter;
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// RIP addressing does not benefit from micro op fusion on Core arch
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@ -136,9 +150,15 @@ struct OpArg
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//if scale == 0 never mind offsetting
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offset = _offset;
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}
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bool operator==(OpArg b)
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{
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return operandReg == b.operandReg && scale == b.scale && offsetOrBaseReg == b.offsetOrBaseReg &&
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indexReg == b.indexReg && offset == b.offset;
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}
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void WriteRex(XEmitter *emit, int opBits, int bits, int customOp = -1) const;
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void WriteVex(XEmitter* emit, int size, int packed, Gen::X64Reg regOp1, X64Reg regOp2) const;
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void WriteRest(XEmitter *emit, int extraBytes=0, X64Reg operandReg=(X64Reg)0xFF, bool warn_64bit_offset = true) const;
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void WriteVex(XEmitter* emit, X64Reg regOp1, X64Reg regOp2, int L, int pp, int mmmmm, int W = 0) const;
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void WriteRest(XEmitter *emit, int extraBytes=0, X64Reg operandReg=INVALID_REG, bool warn_64bit_offset = true) const;
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void WriteFloatModRM(XEmitter *emit, FloatOp op);
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void WriteSingleByteOp(XEmitter *emit, u8 op, X64Reg operandReg, int bits);
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// This one is public - must be written to
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u64 offset; // use RIP-relative as much as possible - 64-bit immediates are not available.
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@ -147,7 +167,8 @@ struct OpArg
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void WriteNormalOp(XEmitter *emit, bool toRM, NormalOp op, const OpArg &operand, int bits) const;
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bool IsImm() const {return scale == SCALE_IMM8 || scale == SCALE_IMM16 || scale == SCALE_IMM32 || scale == SCALE_IMM64;}
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bool IsSimpleReg() const {return scale == SCALE_NONE;}
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bool IsSimpleReg(X64Reg reg) const {
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bool IsSimpleReg(X64Reg reg) const
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{
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if (!IsSimpleReg())
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return false;
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return GetSimpleReg() == reg;
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@ -195,26 +216,35 @@ private:
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u16 indexReg;
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};
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inline OpArg M(void *ptr) {return OpArg((u64)ptr, (int)SCALE_RIP);}
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inline OpArg M(const void *ptr) {return OpArg((u64)ptr, (int)SCALE_RIP);}
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template <typename T>
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inline OpArg M(const T *ptr) {return OpArg((u64)(const void *)ptr, (int)SCALE_RIP);}
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inline OpArg R(X64Reg value) {return OpArg(0, SCALE_NONE, value);}
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inline OpArg MatR(X64Reg value) {return OpArg(0, SCALE_ATREG, value);}
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inline OpArg MDisp(X64Reg value, int offset) {
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inline OpArg MDisp(X64Reg value, int offset)
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{
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return OpArg((u32)offset, SCALE_ATREG, value);
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}
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inline OpArg MComplex(X64Reg base, X64Reg scaled, int scale, int offset) {
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inline OpArg MComplex(X64Reg base, X64Reg scaled, int scale, int offset)
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{
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return OpArg(offset, scale, base, scaled);
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}
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inline OpArg MScaled(X64Reg scaled, int scale, int offset) {
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inline OpArg MScaled(X64Reg scaled, int scale, int offset)
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{
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if (scale == SCALE_1)
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return OpArg(offset, SCALE_ATREG, scaled);
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else
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return OpArg(offset, scale | 0x20, RAX, scaled);
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}
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inline OpArg MRegSum(X64Reg base, X64Reg offset) {
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inline OpArg MRegSum(X64Reg base, X64Reg offset)
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{
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return MComplex(base, offset, 1, 0);
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}
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inline OpArg Imm8 (u8 imm) {return OpArg(imm, SCALE_IMM8);}
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inline OpArg Imm16(u16 imm) {return OpArg(imm, SCALE_IMM16);} //rarely used
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inline OpArg Imm32(u32 imm) {return OpArg(imm, SCALE_IMM32);}
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@ -226,19 +256,23 @@ inline OpArg SImmAuto(s32 imm) {
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return OpArg(imm, (imm >= 128 || imm < -128) ? SCALE_IMM32 : SCALE_IMM8);
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}
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#ifdef _M_X64
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#ifdef _ARCH_64
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inline OpArg ImmPtr(const void* imm) {return Imm64((u64)imm);}
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#else
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inline OpArg ImmPtr(const void* imm) {return Imm32((u32)imm);}
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#endif
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inline u32 PtrOffset(const void* ptr, const void* base) {
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#ifdef _M_X64
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inline u32 PtrOffset(const void* ptr, const void* base)
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{
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#ifdef _ARCH_64
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s64 distance = (s64)ptr-(s64)base;
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if (distance >= 0x80000000LL ||
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distance < -0x80000000LL) {
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_assert_msg_(JIT, 0, "pointer offset out of range");
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distance < -0x80000000LL)
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{
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_assert_msg_(DYNA_REC, 0, "pointer offset out of range");
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return 0;
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}
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return (u32)distance;
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#else
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return (u32)ptr-(u32)base;
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@ -275,21 +309,31 @@ class XEmitter
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friend struct OpArg; // for Write8 etc
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private:
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u8 *code;
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bool flags_locked;
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void CheckFlags();
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void Rex(int w, int r, int x, int b);
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void WriteSimple1Byte(int bits, u8 byte, X64Reg reg);
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void WriteSimple2Byte(int bits, u8 byte1, u8 byte2, X64Reg reg);
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void WriteMulDivType(int bits, OpArg src, int ext);
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void WriteBitSearchType(int bits, X64Reg dest, OpArg src, u8 byte2);
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void WriteBitSearchType(int bits, X64Reg dest, OpArg src, u8 byte2, bool rep = false);
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void WriteShift(int bits, OpArg dest, OpArg &shift, int ext);
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void WriteBitTest(int bits, OpArg &dest, OpArg &index, int ext);
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void WriteMXCSR(OpArg arg, int ext);
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void WriteSSEOp(int size, u8 sseOp, bool packed, X64Reg regOp, OpArg arg, int extrabytes = 0);
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void WriteSSEOp2(int size, u8 sseOp, bool packed, X64Reg regOp, OpArg arg, int extrabytes = 0);
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void WriteAVXOp(int size, u8 sseOp, bool packed, X64Reg regOp, OpArg arg, int extrabytes = 0);
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void WriteAVXOp(int size, u8 sseOp, bool packed, X64Reg regOp1, X64Reg regOp2, OpArg arg, int extrabytes = 0);
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void WriteSSEOp(u8 opPrefix, u16 op, X64Reg regOp, OpArg arg, int extrabytes = 0);
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void WriteSSSE3Op(u8 opPrefix, u16 op, X64Reg regOp, OpArg arg, int extrabytes = 0);
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void WriteSSE41Op(u8 opPrefix, u16 op, X64Reg regOp, OpArg arg, int extrabytes = 0);
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void WriteAVXOp(u8 opPrefix, u16 op, X64Reg regOp, OpArg arg, int extrabytes = 0);
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void WriteAVXOp(u8 opPrefix, u16 op, X64Reg regOp1, X64Reg regOp2, OpArg arg, int extrabytes = 0);
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void WriteVEXOp(int size, u8 opPrefix, u16 op, X64Reg regOp1, X64Reg regOp2, OpArg arg, int extrabytes = 0);
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void WriteBMI1Op(int size, u8 opPrefix, u16 op, X64Reg regOp1, X64Reg regOp2, OpArg arg, int extrabytes = 0);
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void WriteBMI2Op(int size, u8 opPrefix, u16 op, X64Reg regOp1, X64Reg regOp2, OpArg arg, int extrabytes = 0);
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void WriteFloatLoadStore(int bits, FloatOp op, FloatOp op_80b, OpArg arg);
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void WriteNormalOp(XEmitter *emit, int bits, NormalOp op, const OpArg &a1, const OpArg &a2);
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void ABI_CalculateFrameSize(u32 mask, size_t rsp_alignment, size_t needed_frame_size, size_t* shadowp, size_t* subtractionp, size_t* xmm_offsetp);
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protected:
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inline void Write8(u8 value) {*code++ = value;}
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inline void Write16(u16 value) {*(u16*)code = (value); code += 2;}
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@ -297,8 +341,8 @@ protected:
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inline void Write64(u64 value) {*(u64*)code = (value); code += 8;}
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public:
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XEmitter() { code = NULL; }
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XEmitter(u8 *code_ptr) { code = code_ptr; }
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XEmitter() { code = nullptr; flags_locked = false; }
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XEmitter(u8 *code_ptr) { code = code_ptr; flags_locked = false; }
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virtual ~XEmitter() {}
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void WriteModRM(int mod, int rm, int reg);
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@ -312,6 +356,9 @@ public:
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const u8 *GetCodePtr() const;
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u8 *GetWritableCodePtr();
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void LockFlags() { flags_locked = true; }
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void UnlockFlags() { flags_locked = false; }
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// Looking for one of these? It's BANNED!! Some instructions are slow on modern CPU
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// INC, DEC, LOOP, LOOPNE, LOOPE, ENTER, LEAVE, XCHG, XLAT, REP MOVSB/MOVSD, REP SCASD + other string instr.,
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// INC and DEC are slow on Intel Core, but not on AMD. They create a
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@ -322,7 +369,7 @@ public:
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void INT3();
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// Do nothing
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void NOP(int count = 1); //nop padding - TODO: fast nop slides, for amd and intel (check their manuals)
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void NOP(size_t count = 1);
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// Save energy in wait-loops on P4 only. Probably not too useful.
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void PAUSE();
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@ -459,6 +506,14 @@ public:
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void MOVSX(int dbits, int sbits, X64Reg dest, OpArg src); //automatically uses MOVSXD if necessary
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void MOVZX(int dbits, int sbits, X64Reg dest, OpArg src);
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// Available only on Atom or >= Haswell so far. Test with cpu_info.bMOVBE.
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void MOVBE(int dbits, const OpArg& dest, const OpArg& src);
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// Available only on AMD >= Phenom or Intel >= Haswell
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void LZCNT(int bits, X64Reg dest, OpArg src);
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// Note: this one is actually part of BMI1
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void TZCNT(int bits, X64Reg dest, OpArg src);
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// WARNING - These two take 11-13 cycles and are VectorPath! (AMD64)
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void STMXCSR(OpArg memloc);
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void LDMXCSR(OpArg memloc);
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@ -467,7 +522,31 @@ public:
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void LOCK();
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void REP();
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void REPNE();
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void FSOverride();
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void GSOverride();
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// x87
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enum x87StatusWordBits {
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x87_InvalidOperation = 0x1,
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x87_DenormalizedOperand = 0x2,
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x87_DivisionByZero = 0x4,
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x87_Overflow = 0x8,
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x87_Underflow = 0x10,
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x87_Precision = 0x20,
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x87_StackFault = 0x40,
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x87_ErrorSummary = 0x80,
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x87_C0 = 0x100,
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x87_C1 = 0x200,
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x87_C2 = 0x400,
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x87_TopOfStack = 0x2000 | 0x1000 | 0x800,
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x87_C3 = 0x4000,
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x87_FPUBusy = 0x8000,
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};
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void FLD(int bits, OpArg src);
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void FST(int bits, OpArg dest);
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void FSTP(int bits, OpArg dest);
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void FNSTSW_AX();
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void FWAIT();
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// SSE/SSE2: Floating point arithmetic
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@ -490,14 +569,6 @@ public:
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// SSE/SSE2: Floating point bitwise (yes)
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void CMPSS(X64Reg regOp, OpArg arg, u8 compare);
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void CMPSD(X64Reg regOp, OpArg arg, u8 compare);
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void ANDSS(X64Reg regOp, OpArg arg);
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void ANDSD(X64Reg regOp, OpArg arg);
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void ANDNSS(X64Reg regOp, OpArg arg);
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void ANDNSD(X64Reg regOp, OpArg arg);
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void ORSS(X64Reg regOp, OpArg arg);
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void ORSD(X64Reg regOp, OpArg arg);
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void XORSS(X64Reg regOp, OpArg arg);
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void XORSD(X64Reg regOp, OpArg arg);
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inline void CMPEQSS(X64Reg regOp, OpArg arg) { CMPSS(regOp, arg, CMP_EQ); }
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inline void CMPLTSS(X64Reg regOp, OpArg arg) { CMPSS(regOp, arg, CMP_LT); }
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@ -543,11 +614,8 @@ public:
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// SSE/SSE2: Useful alternative to shuffle in some cases.
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void MOVDDUP(X64Reg regOp, OpArg arg);
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// THESE TWO ARE NEW AND UNTESTED
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void UNPCKLPS(X64Reg dest, OpArg src);
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void UNPCKHPS(X64Reg dest, OpArg src);
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// These are OK.
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void UNPCKLPD(X64Reg dest, OpArg src);
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void UNPCKHPD(X64Reg dest, OpArg src);
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@ -568,7 +636,6 @@ public:
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void MOVUPS(OpArg arg, X64Reg regOp);
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void MOVUPD(OpArg arg, X64Reg regOp);
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// Integers (NOTE: untested - I added these then it turned out I didn't have a use for them after all).
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void MOVDQA(X64Reg regOp, OpArg arg);
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void MOVDQA(OpArg arg, X64Reg regOp);
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void MOVDQU(X64Reg regOp, OpArg arg);
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@ -579,6 +646,14 @@ public:
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void MOVSS(OpArg arg, X64Reg regOp);
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void MOVSD(OpArg arg, X64Reg regOp);
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void MOVLPD(X64Reg regOp, OpArg arg);
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void MOVHPD(X64Reg regOp, OpArg arg);
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void MOVLPD(OpArg arg, X64Reg regOp);
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void MOVHPD(OpArg arg, X64Reg regOp);
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void MOVHLPS(X64Reg regOp1, X64Reg regOp2);
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void MOVLHPS(X64Reg regOp1, X64Reg regOp2);
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void MOVD_xmm(X64Reg dest, const OpArg &arg);
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void MOVQ_xmm(X64Reg dest, OpArg arg);
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void MOVD_xmm(const OpArg &arg, X64Reg src);
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@ -596,37 +671,34 @@ public:
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void CVTPS2PD(X64Reg dest, OpArg src);
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void CVTPD2PS(X64Reg dest, OpArg src);
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void CVTSS2SD(X64Reg dest, OpArg src);
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void CVTSI2SS(X64Reg dest, OpArg src);
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void CVTSD2SS(X64Reg dest, OpArg src);
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void CVTSD2SI(X64Reg dest, OpArg src);
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void CVTSI2SD(X64Reg dest, OpArg src);
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void CVTDQ2PD(X64Reg regOp, OpArg arg);
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void CVTPD2DQ(X64Reg regOp, OpArg arg);
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void CVTDQ2PS(X64Reg regOp, OpArg arg);
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void CVTPS2DQ(X64Reg regOp, OpArg arg);
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void CVTTSS2SI(X64Reg xregdest, OpArg arg); // Yeah, destination really is a GPR like EAX!
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void CVTTPS2DQ(X64Reg regOp, OpArg arg);
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void CVTSI2SS(X64Reg xregdest, OpArg arg); // Yeah, destination really is a GPR like EAX!
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void CVTSS2SI(X64Reg xregdest, OpArg arg); // Yeah, destination really is a GPR like EAX!
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void CVTTSD2SI(X64Reg xregdest, OpArg arg); // Yeah, destination really is a GPR like EAX!
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void CVTTPD2DQ(X64Reg xregdest, OpArg arg);
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void CVTTPD2DQ(X64Reg regOp, OpArg arg);
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// Destinations are X64 regs (rax, rbx, ...) for these instructions.
|
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void CVTSS2SI(X64Reg xregdest, OpArg src);
|
||||
void CVTSD2SI(X64Reg xregdest, OpArg src);
|
||||
void CVTTSS2SI(X64Reg xregdest, OpArg arg);
|
||||
void CVTTSD2SI(X64Reg xregdest, OpArg arg);
|
||||
|
||||
// SSE2: Packed integer instructions
|
||||
void PACKSSDW(X64Reg dest, OpArg arg);
|
||||
void PACKSSWB(X64Reg dest, OpArg arg);
|
||||
//void PACKUSDW(X64Reg dest, OpArg arg);
|
||||
void PACKUSDW(X64Reg dest, OpArg arg);
|
||||
void PACKUSWB(X64Reg dest, OpArg arg);
|
||||
|
||||
void PUNPCKLBW(X64Reg dest, const OpArg &arg);
|
||||
void PUNPCKLWD(X64Reg dest, const OpArg &arg);
|
||||
void PUNPCKLDQ(X64Reg dest, const OpArg &arg);
|
||||
|
||||
void PMOVSXBW(X64Reg dest, const OpArg &arg);
|
||||
void PMOVSXBD(X64Reg dest, const OpArg &arg);
|
||||
void PMOVSXWD(X64Reg dest, const OpArg &arg);
|
||||
void PMOVZXBW(X64Reg dest, const OpArg &arg);
|
||||
void PMOVZXBD(X64Reg dest, const OpArg &arg);
|
||||
void PMOVZXWD(X64Reg dest, const OpArg &arg);
|
||||
|
||||
void PTEST(X64Reg dest, OpArg arg);
|
||||
void PAND(X64Reg dest, OpArg arg);
|
||||
void PANDN(X64Reg dest, OpArg arg);
|
||||
void PXOR(X64Reg dest, OpArg arg);
|
||||
@ -680,29 +752,75 @@ public:
|
||||
void PSHUFB(X64Reg dest, OpArg arg);
|
||||
|
||||
void PSHUFLW(X64Reg dest, OpArg arg, u8 shuffle);
|
||||
void PSHUFHW(X64Reg dest, OpArg arg, u8 shuffle);
|
||||
|
||||
void PSRLW(X64Reg reg, int shift);
|
||||
void PSRLD(X64Reg reg, int shift);
|
||||
void PSRLQ(X64Reg reg, int shift);
|
||||
void PSRLQ(X64Reg reg, OpArg arg);
|
||||
void PSRLDQ(X64Reg reg, int shift);
|
||||
|
||||
void PSLLW(X64Reg reg, int shift);
|
||||
void PSLLD(X64Reg reg, int shift);
|
||||
void PSLLQ(X64Reg reg, int shift);
|
||||
|
||||
void PSRLDQ(X64Reg reg, int shift);
|
||||
void PSLLDQ(X64Reg reg, int shift);
|
||||
|
||||
void PSRAW(X64Reg reg, int shift);
|
||||
void PSRAD(X64Reg reg, int shift);
|
||||
|
||||
// SSE4: data type conversions
|
||||
void PMOVSXBW(X64Reg dest, OpArg arg);
|
||||
void PMOVSXBD(X64Reg dest, OpArg arg);
|
||||
void PMOVSXBQ(X64Reg dest, OpArg arg);
|
||||
void PMOVSXWD(X64Reg dest, OpArg arg);
|
||||
void PMOVSXWQ(X64Reg dest, OpArg arg);
|
||||
void PMOVSXDQ(X64Reg dest, OpArg arg);
|
||||
void PMOVZXBW(X64Reg dest, OpArg arg);
|
||||
void PMOVZXBD(X64Reg dest, OpArg arg);
|
||||
void PMOVZXBQ(X64Reg dest, OpArg arg);
|
||||
void PMOVZXWD(X64Reg dest, OpArg arg);
|
||||
void PMOVZXWQ(X64Reg dest, OpArg arg);
|
||||
void PMOVZXDQ(X64Reg dest, OpArg arg);
|
||||
|
||||
// SSE4: variable blend instructions (xmm0 implicit argument)
|
||||
void PBLENDVB(X64Reg dest, OpArg arg);
|
||||
void BLENDVPS(X64Reg dest, OpArg arg);
|
||||
void BLENDVPD(X64Reg dest, OpArg arg);
|
||||
|
||||
// AVX
|
||||
void VADDSD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
|
||||
void VSUBSD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
|
||||
void VMULSD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
|
||||
void VDIVSD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
|
||||
void VADDPD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
|
||||
void VSUBPD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
|
||||
void VMULPD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
|
||||
void VDIVPD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
|
||||
void VSQRTSD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
|
||||
void VPAND(X64Reg regOp1, X64Reg regOp2, OpArg arg);
|
||||
void VPANDN(X64Reg regOp1, X64Reg regOp2, OpArg arg);
|
||||
void VPOR(X64Reg regOp1, X64Reg regOp2, OpArg arg);
|
||||
void VPXOR(X64Reg regOp1, X64Reg regOp2, OpArg arg);
|
||||
void VSHUFPD(X64Reg regOp1, X64Reg regOp2, OpArg arg, u8 shuffle);
|
||||
void VUNPCKLPD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
|
||||
void VUNPCKHPD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
|
||||
|
||||
void RTDSC();
|
||||
// VEX GPR instructions
|
||||
void SARX(int bits, X64Reg regOp1, OpArg arg, X64Reg regOp2);
|
||||
void SHLX(int bits, X64Reg regOp1, OpArg arg, X64Reg regOp2);
|
||||
void SHRX(int bits, X64Reg regOp1, OpArg arg, X64Reg regOp2);
|
||||
void RORX(int bits, X64Reg regOp, OpArg arg, u8 rotate);
|
||||
void PEXT(int bits, X64Reg regOp1, X64Reg regOp2, OpArg arg);
|
||||
void PDEP(int bits, X64Reg regOp1, X64Reg regOp2, OpArg arg);
|
||||
void MULX(int bits, X64Reg regOp1, X64Reg regOp2, OpArg arg);
|
||||
void BZHI(int bits, X64Reg regOp1, OpArg arg, X64Reg regOp2);
|
||||
void BLSR(int bits, X64Reg regOp, OpArg arg);
|
||||
void BLSMSK(int bits, X64Reg regOp, OpArg arg);
|
||||
void BLSI(int bits, X64Reg regOp, OpArg arg);
|
||||
void BEXTR(int bits, X64Reg regOp1, OpArg arg, X64Reg regOp2);
|
||||
void ANDN(int bits, X64Reg regOp1, X64Reg regOp2, OpArg arg);
|
||||
|
||||
void RDTSC();
|
||||
|
||||
// Utility functions
|
||||
// The difference between this and CALL is that this aligns the stack
|
||||
@ -719,6 +837,7 @@ public:
|
||||
void ABI_CallFunctionC16(const void *func, u16 param1);
|
||||
void ABI_CallFunctionCC16(const void *func, u32 param1, u16 param2);
|
||||
|
||||
|
||||
// These only support u32 parameters, but that's enough for a lot of uses.
|
||||
// These will destroy the 1 or 2 first "parameter regs".
|
||||
void ABI_CallFunctionC(const void *func, u32 param1);
|
||||
@ -736,8 +855,8 @@ public:
|
||||
void ABI_CallFunctionAA(const void *func, const Gen::OpArg &arg1, const Gen::OpArg &arg2);
|
||||
|
||||
// Pass a register as a parameter.
|
||||
void ABI_CallFunctionR(const void *func, Gen::X64Reg reg1);
|
||||
void ABI_CallFunctionRR(const void *func, Gen::X64Reg reg1, Gen::X64Reg reg2);
|
||||
void ABI_CallFunctionR(const void *func, X64Reg reg1);
|
||||
void ABI_CallFunctionRR(const void *func, X64Reg reg1, X64Reg reg2);
|
||||
|
||||
template <typename Tr, typename T1>
|
||||
void ABI_CallFunctionC(Tr (*func)(T1), u32 param1) {
|
||||
@ -822,4 +941,4 @@ public:
|
||||
|
||||
} // namespace
|
||||
|
||||
#endif // _DOLPHIN_INTEL_CODEGEN_
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user