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Move tempValues into MIPSState

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This commit is contained in:
Henrik Rydgård 2017-07-05 14:23:52 +02:00
parent f08c278fd5
commit 7c1ae5b3e6
3 changed files with 16 additions and 13 deletions
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9
Core/MIPS/MIPS.h
View File

@ -158,6 +158,10 @@ enum class CPUCore;
#endif
enum {
NUM_X86_FPU_TEMPS = 16,
};
class MIPSState
{
public:
@ -230,6 +234,11 @@ public:
static const u32 FCR0_VALUE = 0x00003351;
#if defined(PPSSPP_ARCH_X86) || defined(PPSSPP_ARCH_AMD64)
// FPU TEMP0, etc. are swapped in here if necessary (e.g. on x86.)
float tempValues[NUM_X86_FPU_TEMPS];
#endif
u8 VfpuWriteMask() const {
return (vfpuCtrl[VFPU_CTRL_DPREFIX] >> 8) & 0xF;
}

14
Core/MIPS/x86/RegCacheFPU.cpp
View File

@ -31,8 +31,6 @@
using namespace Gen;
using namespace X64JitConstants;
float FPURegCache::tempValues[NUM_TEMPS];
FPURegCache::FPURegCache() : mips(0), initialReady(false), emit(0) {
memset(regs, 0, sizeof(regs));
memset(xregs, 0, sizeof(xregs));
@ -416,7 +414,7 @@ X64Reg FPURegCache::LoadRegsVS(const u8 *v, int n) {
break;
}
}
const float *f = v[0] < 128 ? &mips->v[voffset[v[0]]] : &tempValues[v[0] - 128];
const float *f = v[0] < 128 ? &mips->v[voffset[v[0]]] : &mips->tempValues[v[0] - 128];
if (((intptr_t)f & 0x7) == 0 && n == 2) {
emit->MOVQ_xmm(res, vregs[v[0]].location);
} else if (((intptr_t)f & 0xf) == 0) {
@ -599,7 +597,7 @@ void FPURegCache::ReleaseSpillLock(int mipsreg) {
void FPURegCache::ReleaseSpillLocks() {
for (int i = 0; i < NUM_MIPS_FPRS; i++)
regs[i].locked = 0;
for (int i = TEMP0; i < TEMP0 + NUM_TEMPS; ++i)
for (int i = TEMP0; i < TEMP0 + NUM_X86_FPU_TEMPS; ++i)
DiscardR(i);
}
@ -675,7 +673,7 @@ void FPURegCache::StoreFromRegister(int i) {
}
}
const float *f = mri[0] - 32 < 128 ? &mips->v[voffset[mri[0] - 32]] : &tempValues[mri[0] - 32 - 128];
const float *f = mri[0] - 32 < 128 ? &mips->v[voffset[mri[0] - 32]] : &mips->tempValues[mri[0] - 32 - 128];
int align = (intptr_t)f & 0xf;
// If we can do a multistore...
@ -811,7 +809,7 @@ bool FPURegCache::IsTempX(X64Reg xr) {
int FPURegCache::GetTempR() {
pendingFlush = true;
for (int r = TEMP0; r < TEMP0 + NUM_TEMPS; ++r) {
for (int r = TEMP0; r < TEMP0 + NUM_X86_FPU_TEMPS; ++r) {
if (!regs[r].away && !regs[r].tempLocked) {
regs[r].tempLocked = true;
return r;
@ -828,7 +826,7 @@ int FPURegCache::GetTempVS(u8 *v, VectorSize vsz) {
// Let's collect regs as we go, but try for n free in a row.
int found = 0;
for (int r = TEMP0; r <= TEMP0 + NUM_TEMPS - n; ++r) {
for (int r = TEMP0; r <= TEMP0 + NUM_X86_FPU_TEMPS - n; ++r) {
if (regs[r].away || regs[r].tempLocked) {
continue;
}
@ -900,7 +898,7 @@ OpArg FPURegCache::GetDefaultLocation(int reg) const {
// This should work, but doesn't seem to. Maybe used from somewhere where CTXREG is not yet set properly.
// return MDisp(CTXREG, offsetof(MIPSState, v[0]) - offsetof(MIPSState, f[0]) + voffset[reg - 32] * sizeof(float));
} else {
return M(&tempValues[reg - 32 - 128]);
return M(&mips->tempValues[reg - 32 - 128]);
}
}

6
Core/MIPS/x86/RegCacheFPU.h
View File

@ -44,9 +44,8 @@
// and do it the old way.
enum {
NUM_TEMPS = 16,
TEMP0 = 32 + 128,
NUM_MIPS_FPRS = 32 + 128 + NUM_TEMPS,
NUM_MIPS_FPRS = 32 + 128 + NUM_X86_FPU_TEMPS,
};
#ifdef _M_X64
@ -237,9 +236,6 @@ private:
MIPSCachedFPReg regsInitial[NUM_MIPS_FPRS];
X64CachedFPReg xregsInitial[NUM_X_FPREGS];
// TEMP0, etc. are swapped in here if necessary (e.g. on x86.)
static float tempValues[NUM_TEMPS];
Gen::XEmitter *emit;
MIPSComp::JitState *js_;
MIPSComp::JitOptions *jo_;