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jit: Avoid mfhi/mflo to $0.

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This commit is contained in:
Unknown W. Brackets 2015-04-07 18:25:28 -07:00
parent 788b9d78f8
commit 7ce5841f30
3 changed files with 24 additions and 16 deletions
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24
Core/MIPS/ARM/ArmCompALU.cpp
View File

@ -680,12 +680,14 @@ namespace MIPSComp
switch (op & 63) {
case 16: // R(rd) = HI; //mfhi
if (gpr.IsImm(MIPS_REG_HI)) {
gpr.SetImm(rd, gpr.GetImm(MIPS_REG_HI));
break;
if (rd != MIPS_REG_ZERO) {
if (gpr.IsImm(MIPS_REG_HI)) {
gpr.SetImm(rd, gpr.GetImm(MIPS_REG_HI));
break;
}
gpr.MapDirtyIn(rd, MIPS_REG_HI);
MOV(gpr.R(rd), gpr.R(MIPS_REG_HI));
}
gpr.MapDirtyIn(rd, MIPS_REG_HI);
MOV(gpr.R(rd), gpr.R(MIPS_REG_HI));
break;
case 17: // HI = R(rs); //mthi
@ -698,12 +700,14 @@ namespace MIPSComp
break;
case 18: // R(rd) = LO; break; //mflo
if (gpr.IsImm(MIPS_REG_LO)) {
gpr.SetImm(rd, gpr.GetImm(MIPS_REG_LO));
break;
if (rd != MIPS_REG_ZERO) {
if (gpr.IsImm(MIPS_REG_LO)) {
gpr.SetImm(rd, gpr.GetImm(MIPS_REG_LO));
break;
}
gpr.MapDirtyIn(rd, MIPS_REG_LO);
MOV(gpr.R(rd), gpr.R(MIPS_REG_LO));
}
gpr.MapDirtyIn(rd, MIPS_REG_LO);
MOV(gpr.R(rd), gpr.R(MIPS_REG_LO));
break;
case 19: // LO = R(rs); break; //mtlo

4
Core/MIPS/MIPSInt.cpp
View File

@ -662,9 +662,9 @@ namespace MIPSInt
HI = (u32)(result>>32);
}
break;
case 16: R(rd) = HI; break; //mfhi
case 16: if (rd != 0) R(rd) = HI; break; //mfhi
case 17: HI = R(rs); break; //mthi
case 18: R(rd) = LO; break; //mflo
case 18: if (rd != 0) R(rd) = LO; break; //mflo
case 19: LO = R(rs); break; //mtlo
case 26: //div
{

12
Core/MIPS/x86/CompALU.cpp
View File

@ -943,8 +943,10 @@ namespace MIPSComp
switch (op & 63)
{
case 16: // R(rd) = HI; //mfhi
gpr.MapReg(rd, false, true);
MOV(32, gpr.R(rd), gpr.R(MIPS_REG_HI));
if (rd != MIPS_REG_ZERO) {
gpr.MapReg(rd, false, true);
MOV(32, gpr.R(rd), gpr.R(MIPS_REG_HI));
}
break;
case 17: // HI = R(rs); //mthi
@ -954,8 +956,10 @@ namespace MIPSComp
break;
case 18: // R(rd) = LO; break; //mflo
gpr.MapReg(rd, false, true);
MOV(32, gpr.R(rd), gpr.R(MIPS_REG_LO));
if (rd != MIPS_REG_ZERO) {
gpr.MapReg(rd, false, true);
MOV(32, gpr.R(rd), gpr.R(MIPS_REG_LO));
}
break;
case 19: // LO = R(rs); break; //mtlo