From 7ce5841f303342e827c31b342a3751ef56ea48bd Mon Sep 17 00:00:00 2001
From: "Unknown W. Brackets" <checkins@unknownbrackets.org>
Date: Tue, 7 Apr 2015 18:25:28 -0700
Subject: [PATCH] jit: Avoid mfhi/mflo to $0.

---
 Core/MIPS/ARM/ArmCompALU.cpp | 24 ++++++++++++++----------
 Core/MIPS/MIPSInt.cpp        |  4 ++--
 Core/MIPS/x86/CompALU.cpp    | 12 ++++++++----
 3 files changed, 24 insertions(+), 16 deletions(-)

diff --git a/Core/MIPS/ARM/ArmCompALU.cpp b/Core/MIPS/ARM/ArmCompALU.cpp
index abe5d244b0..9e08567670 100644
--- a/Core/MIPS/ARM/ArmCompALU.cpp
+++ b/Core/MIPS/ARM/ArmCompALU.cpp
@@ -680,12 +680,14 @@ namespace MIPSComp
 
 		switch (op & 63) {
 		case 16: // R(rd) = HI; //mfhi
-			if (gpr.IsImm(MIPS_REG_HI)) {
-				gpr.SetImm(rd, gpr.GetImm(MIPS_REG_HI));
-				break;
+			if (rd != MIPS_REG_ZERO) {
+				if (gpr.IsImm(MIPS_REG_HI)) {
+					gpr.SetImm(rd, gpr.GetImm(MIPS_REG_HI));
+					break;
+				}
+				gpr.MapDirtyIn(rd, MIPS_REG_HI);
+				MOV(gpr.R(rd), gpr.R(MIPS_REG_HI));
 			}
-			gpr.MapDirtyIn(rd, MIPS_REG_HI);
-			MOV(gpr.R(rd), gpr.R(MIPS_REG_HI));
 			break; 
 
 		case 17: // HI = R(rs); //mthi
@@ -698,12 +700,14 @@ namespace MIPSComp
 			break; 
 
 		case 18: // R(rd) = LO; break; //mflo
-			if (gpr.IsImm(MIPS_REG_LO)) {
-				gpr.SetImm(rd, gpr.GetImm(MIPS_REG_LO));
-				break;
+			if (rd != MIPS_REG_ZERO) {
+				if (gpr.IsImm(MIPS_REG_LO)) {
+					gpr.SetImm(rd, gpr.GetImm(MIPS_REG_LO));
+					break;
+				}
+				gpr.MapDirtyIn(rd, MIPS_REG_LO);
+				MOV(gpr.R(rd), gpr.R(MIPS_REG_LO));
 			}
-			gpr.MapDirtyIn(rd, MIPS_REG_LO);
-			MOV(gpr.R(rd), gpr.R(MIPS_REG_LO));
 			break;
 
 		case 19: // LO = R(rs); break; //mtlo
diff --git a/Core/MIPS/MIPSInt.cpp b/Core/MIPS/MIPSInt.cpp
index 8c82e4b7a8..0830894781 100644
--- a/Core/MIPS/MIPSInt.cpp
+++ b/Core/MIPS/MIPSInt.cpp
@@ -662,9 +662,9 @@ namespace MIPSInt
 				HI = (u32)(result>>32);
 			}
 			break;
-		case 16: R(rd) = HI; break; //mfhi
+		case 16: if (rd != 0) R(rd) = HI; break; //mfhi
 		case 17: HI = R(rs); break; //mthi
-		case 18: R(rd) = LO; break; //mflo
+		case 18: if (rd != 0) R(rd) = LO; break; //mflo
 		case 19: LO = R(rs); break; //mtlo
 		case 26: //div
 			{
diff --git a/Core/MIPS/x86/CompALU.cpp b/Core/MIPS/x86/CompALU.cpp
index ec54fc41af..39e753039b 100644
--- a/Core/MIPS/x86/CompALU.cpp
+++ b/Core/MIPS/x86/CompALU.cpp
@@ -943,8 +943,10 @@ namespace MIPSComp
 		switch (op & 63) 
 		{
 		case 16: // R(rd) = HI; //mfhi
-			gpr.MapReg(rd, false, true);
-			MOV(32, gpr.R(rd), gpr.R(MIPS_REG_HI));
+			if (rd != MIPS_REG_ZERO) {
+				gpr.MapReg(rd, false, true);
+				MOV(32, gpr.R(rd), gpr.R(MIPS_REG_HI));
+			}
 			break; 
 
 		case 17: // HI = R(rs); //mthi
@@ -954,8 +956,10 @@ namespace MIPSComp
 			break; 
 
 		case 18: // R(rd) = LO; break; //mflo
-			gpr.MapReg(rd, false, true);
-			MOV(32, gpr.R(rd), gpr.R(MIPS_REG_LO));
+			if (rd != MIPS_REG_ZERO) {
+				gpr.MapReg(rd, false, true);
+				MOV(32, gpr.R(rd), gpr.R(MIPS_REG_LO));
+			}
 			break;
 
 		case 19: // LO = R(rs); break; //mtlo