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More progress but it weirds out...

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This commit is contained in:
Henrik Rydgard 2013-01-08 21:24:42 +01:00
parent e3a4ed510c
commit 8915677241
14 changed files with 148 additions and 113 deletions
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10
Common/ArmABI.cpp
View File

@ -23,15 +23,15 @@ using namespace ArmGen;
// If passing arguments, don't use this.
void ARMXEmitter::ARMABI_CallFunction(void *func)
{
ARMABI_MOVI2R(R14, Mem(func));
PUSH(5, R0, R1, R2, R3, _LR);
ARMABI_MOVI2R(R14, Mem(func));
BL(R14);
POP(5, R0, R1, R2, R3, _LR);
}
void ARMXEmitter::ARMABI_CallFunctionC(void *func, u32 Arg)
{
ARMABI_MOVI2R(R14, Mem(func));
PUSH(5, R0, R1, R2, R3, _LR);
ARMABI_MOVI2R(R14, Mem(func));
ARMABI_MOVI2R(R0, Arg);
BL(R14);
POP(5, R0, R1, R2, R3, _LR);
@ -39,8 +39,8 @@ void ARMXEmitter::ARMABI_CallFunctionC(void *func, u32 Arg)
void ARMXEmitter::ARMABI_CallFunctionCNoSave(void *func, u32 Arg)
{
ARMABI_MOVI2R(R14, Mem(func));
PUSH(1, _LR);
ARMABI_MOVI2R(R14, Mem(func));
ARMABI_MOVI2R(R0, Arg);
BL(R14);
POP(1, _LR);
@ -48,8 +48,8 @@ void ARMXEmitter::ARMABI_CallFunctionCNoSave(void *func, u32 Arg)
void ARMXEmitter::ARMABI_CallFunctionCC(void *func, u32 Arg1, u32 Arg2)
{
ARMABI_MOVI2R(R14, Mem(func));
PUSH(5, R0, R1, R2, R3, _LR);
ARMABI_MOVI2R(R14, Mem(func));
ARMABI_MOVI2R(R0, Arg1);
ARMABI_MOVI2R(R1, Arg2);
BL(R14);
@ -58,8 +58,8 @@ void ARMXEmitter::ARMABI_CallFunctionCC(void *func, u32 Arg1, u32 Arg2)
}
void ARMXEmitter::ARMABI_CallFunctionCCC(void *func, u32 Arg1, u32 Arg2, u32 Arg3)
{
ARMABI_MOVI2R(R14, Mem(func));
PUSH(5, R0, R1, R2, R3, _LR);
ARMABI_MOVI2R(R14, Mem(func));
ARMABI_MOVI2R(R0, Arg1);
ARMABI_MOVI2R(R1, Arg2);
ARMABI_MOVI2R(R2, Arg3);

2
Common/LogManager.cpp
View File

@ -149,6 +149,8 @@ void LogManager::LoadConfig(IniFile::Section *section)
void LogManager::Log(LogTypes::LOG_LEVELS level, LogTypes::LOG_TYPE type, const char *file, int line, const char *format, va_list args)
{
std::lock_guard<std::mutex> lk(m_log_lock);
char temp[MAX_MSGLEN];
char msg[MAX_MSGLEN * 2];
LogContainer *log = m_Log[type];

1
Common/LogManager.h
View File

@ -106,6 +106,7 @@ private:
ConsoleListener *m_consoleLog;
DebuggerLogListener *m_debuggerLog;
static LogManager *m_logManager; // Singleton. Ugh.
std::mutex m_log_lock;
LogManager();
~LogManager();

2
Core/Core.cpp
View File

@ -65,6 +65,7 @@ bool Core_IsStepping()
void Core_RunLoop()
{
currentMIPS->RunLoopUntil(0xFFFFFFFFFFFFFFFULL);
INFO_LOG(DYNA_REC, "Wooo");
}
void Core_DoSingleStep()
@ -93,6 +94,7 @@ reswitch:
case CORE_RUNNING:
//1: enter a fast runloop
Core_RunLoop();
INFO_LOG(DYNA_REC, "Yay");
break;
// We should never get here on Android.

1
Core/CoreTiming.cpp
View File

@ -462,6 +462,7 @@ void MoveEvents()
void Advance()
{
WARN_LOG(HLE, "ADVANCE!");
int cyclesExecuted = slicelength - downcount;
globalTimer += cyclesExecuted;
downcount = slicelength;

1
Core/HLE/sceDisplay.cpp
View File

@ -269,6 +269,7 @@ void hleEnterVblank(u64 userdata, int cyclesLate) {
// Tell the emu core that it's time to stop emulating
// Win32 doesn't need this.
#ifndef _WIN32
ERROR_LOG(HLE, "End oph phrame");
coreState = CORE_NEXTFRAME;
#endif
}

41
Core/MIPS/ARM/ArmAsm.cpp
View File

@ -62,20 +62,19 @@ extern volatile CoreState coreState;
void Jit()
{
INFO_LOG(HLE, "Compiling at %08x", currentMIPS->pc);
MIPSComp::jit->Compile(currentMIPS->pc);
}
void ImHere() {
static int i = 0;
i++;
INFO_LOG(HLE, "I'm too here %i", i);
}
void ImHere2(u32 hej, u32 hej2) {
static int i = 0;
i++;
INFO_LOG(HLE, "I'm here2 %i %08x %08x", i, hej, hej2);
void ShowPC() {
if (currentMIPS) {
WARN_LOG(HLE, "PC : %08x", currentMIPS->pc);
} else {
ERROR_LOG(HLE, "Universe corrupt?");
}
}
void DisassembleArm(const u8 *data, int size);
// PLAN: no more block numbers - crazy opcodes just contain offset within
// dynarec buffer
// At this offset - 4, there is an int specifying the block number.
@ -88,7 +87,7 @@ void ArmAsmRoutineManager::Generate(MIPSState *mips, MIPSComp::Jit *jit)
SetCC(CC_AL);
PUSH(8, R5, R6, R7, R8, R9, R10, R11, _LR);
PUSH(9, R4, R5, R6, R7, R8, R9, R10, R11, _LR);
// Fixed registers, these are always kept when in Jit context.
// R13 cannot be used as it's the stack pointer.
@ -96,9 +95,6 @@ void ArmAsmRoutineManager::Generate(MIPSState *mips, MIPSComp::Jit *jit)
ARMABI_MOVI2R(R10, (u32)mips);
ARMABI_MOVI2R(R9, (u32)jit->GetBlockCache()->GetCodePointers());
// PROVEN: We Get Here
ARMABI_CallFunction((void *)&ImHere);
outerLoop = GetCodePtr();
ARMABI_CallFunction((void *)&CoreTiming::Advance);
FixupBranch skipToRealDispatch = B(); //skip the sync and compare first time
@ -114,18 +110,19 @@ void ArmAsmRoutineManager::Generate(MIPSState *mips, MIPSComp::Jit *jit)
// At this point : flags = EQ. Fine for the next check, no need to jump over it.
dispatcher = GetCodePtr();
// The result of slice decrementation should be in flags if somebody jumped here
// IMPORTANT - We jump on negative, not carry!!!
FixupBranch bail = B_CC(CC_LT);
FixupBranch bail = B_CC(CC_MI);
SetJumpTarget(skipToRealDispatch);
dispatcherNoCheck = GetCodePtr();
// Debug
// ARMABI_CallFunction((void *)&ShowPC);
ARMABI_MOVI2R(R0, (u32)&mips->pc);
LDR(R0, R0);
LDR(R0, R10, offsetof(MIPSState, pc));
ARMABI_MOVI2R(R1, Memory::MEMVIEW32_MASK); // can be done with single MOVN instruction
AND(R0, R0, R1);
@ -134,7 +131,7 @@ void ArmAsmRoutineManager::Generate(MIPSState *mips, MIPSComp::Jit *jit)
AND(R1, R0, Operand2(0xFC, 4)); // rotation is to the right, in 2-bit increments.
BIC(R0, R0, Operand2(0xFC, 4));
CMP(R1, Operand2(MIPS_EMUHACK_OPCODE >> 24, 4));
FixupBranch notfound = B_CC(CC_NEQ);
FixupBranch notfound = B_CC(CC_NEQ); // TODO : No need for a branch really, can use CCs.
// IDEA - we have 24 bits, why not just use offsets from base of code?
if (enableDebug)
{
@ -162,9 +159,11 @@ void ArmAsmRoutineManager::Generate(MIPSState *mips, MIPSComp::Jit *jit)
SetJumpTarget(badCoreState);
ARMABI_CallFunction((void *)&ImHere);
breakpointBailout = GetCodePtr();
//Landing pad for drec space
POP(9, R4, R5, R6, R7, R8, R9, R10, R11, _PC); // Returns
POP(8, R5, R6, R7, R8, R9, R10, R11, _PC); // Returns
INFO_LOG(HLE, "THE DISASM ========================");
DisassembleArm(enterCode, GetCodePtr() - enterCode);
INFO_LOG(HLE, "END OF THE DISASM ========================");
}

88
Core/MIPS/ARM/ArmCompBranch.cpp
View File

@ -44,6 +44,10 @@ namespace MIPSComp
void Jit::BranchRSRTComp(u32 op, ArmGen::CCFlags cc, bool likely)
{
if (js.inDelaySlot) {
ERROR_LOG(JIT, "Branch in delay slot at %08x", js.compilerPC);
return;
}
int offset = (signed short)(op&0xFFFF)<<2;
int rt = _RT;
int rs = _RS;
@ -52,24 +56,25 @@ void Jit::BranchRSRTComp(u32 op, ArmGen::CCFlags cc, bool likely)
u32 delaySlotOp = Memory::ReadUnchecked_U32(js.compilerPC+4);
//Compile the delay slot
bool delaySlotIsNice = GetOutReg(delaySlotOp) != rt && GetOutReg(delaySlotOp) != rs;// IsDelaySlotNice(op, delaySlotOp);
bool delaySlotIsNice = GetOutReg(delaySlotOp) != rt && GetOutReg(delaySlotOp) != rs;
if (!delaySlotIsNice)
{
//ERROR_LOG(CPU, "Not nice delay slot in BranchRSRTComp :( %08x", js.compilerPC);
}
// The delay slot being nice doesn't really matter though...
/*
if (rt == 0)
{
gpr.MapReg(rs, MAP_INITVAL);
CMP(gpr.R(rs), Operand2(0));
}
}*/
/*
else if (rs == 0 && (cc == CC_EQ || cc == CC_NEQ)) // only these are easily 'flippable'
{
gpr.MapReg(rt, MAP_INITVAL);
CMP(gpr.R(rt), Operand2(0));
}*/
else
}
else*/
{
gpr.SpillLock(rs, rt);
gpr.MapReg(rs, MAP_INITVAL);
@ -86,10 +91,11 @@ void Jit::BranchRSRTComp(u32 op, ArmGen::CCFlags cc, bool likely)
// preserve flag around the delay slot! Maybe this is not always necessary on ARM where
// we can (mostly) control whether we set the flag or not. Of course, if someone puts an slt in to the
// delay slot, we're screwed.
MRS(R8); // Save flags register. R4 is preserved through function calls and is not allocated.
MRS(R8); // Save flags register. R8 is preserved through function calls and is not allocated.
CompileAt(js.compilerPC + 4);
FlushAll();
_MSR(true, false, R8); // Restore flags register
ptr = B_CC(cc);
}
else
@ -113,6 +119,10 @@ void Jit::BranchRSRTComp(u32 op, ArmGen::CCFlags cc, bool likely)
void Jit::BranchRSZeroComp(u32 op, ArmGen::CCFlags cc, bool likely)
{
if (js.inDelaySlot) {
ERROR_LOG(JIT, "Branch in delay slot at %08x", js.compilerPC);
return;
}
int offset = (signed short)(op&0xFFFF)<<2;
int rs = _RS;
u32 targetAddr = js.compilerPC + offset + 4;
@ -128,8 +138,8 @@ void Jit::BranchRSZeroComp(u32 op, ArmGen::CCFlags cc, bool likely)
CMP(gpr.R(rs), Operand2(0));
FlushAll();
js.inDelaySlot = true;
ArmGen::FixupBranch ptr;
js.inDelaySlot = true;
if (!likely)
{
// preserve flag around the delay slot! Maybe this is not always necessary on ARM where
@ -201,6 +211,10 @@ void Jit::Comp_RelBranchRI(u32 op)
// If likely is set, discard the branch slot if NOT taken.
void Jit::BranchFPFlag(u32 op, ArmGen::CCFlags cc, bool likely)
{
if (js.inDelaySlot) {
ERROR_LOG(JIT, "Branch in delay slot at %08x", js.compilerPC);
return;
}
int offset = (signed short)(op & 0xFFFF) << 2;
u32 targetAddr = js.compilerPC + offset + 4;
@ -322,11 +336,19 @@ void Jit::Comp_VBranch(u32 op)
js.compiling = false;
}
void PrintAtExit() {
INFO_LOG(HLE, "at jump");
}
void Jit::Comp_Jump(u32 op)
{
u32 off = ((op & 0x3FFFFFF) << 2);
if (js.inDelaySlot) {
ERROR_LOG(JIT, "Branch in delay slot at %08x", js.compilerPC);
return;
}
u32 off = ((op & 0x03FFFFFF) << 2);
u32 targetAddr = (js.compilerPC & 0xF0000000) | off;
//Delay slot
// Delay slot
CompileAt(js.compilerPC + 4);
FlushAll();
@ -337,8 +359,8 @@ void Jit::Comp_Jump(u32 op)
break;
case 3: //jal
ARMABI_MOVI2R(R0, Operand2(js.compilerPC + 8, TYPE_IMM));
ADD(R1, R10, MIPS_REG_RA * 4); // compute address of RA in ram
ARMABI_MOVI2R(R0, js.compilerPC + 8);
STR(R1, R0);
WriteExit(targetAddr, 0);
break;
@ -352,34 +374,51 @@ void Jit::Comp_Jump(u32 op)
void Jit::Comp_JumpReg(u32 op)
{
u32 delaySlotOp = Memory::ReadUnchecked_U32(js.compilerPC + 4);
bool delaySlotIsNice = GetOutReg(delaySlotOp) != _RS;
// Do what with that information?
if (js.inDelaySlot) {
ERROR_LOG(JIT, "Branch in delay slot at %08x", js.compilerPC);
return;
}
int rs = _RS;
u32 delaySlotOp = Memory::ReadUnchecked_U32(js.compilerPC + 4);
bool delaySlotIsNice = GetOutReg(delaySlotOp) != rs;
// Do what with that information?
delaySlotIsNice = false;
gpr.MapReg(rs, MAP_INITVAL);
// Delay slot
MOV(R8, gpr.R(rs)); // Save the destination address through the delay slot. Could use isNice to avoid
CompileAt(js.compilerPC + 4);
FlushAll();
MOV(R0, R8); // TODO: Remove.
if (delaySlotIsNice) {
CompileAt(js.compilerPC + 4);
MOV(R8, gpr.R(rs)); // Save the destination address through the delay slot. Could use isNice to avoid when the jit is fully implemented
FlushAll();
MovToPC(R8); // For syscall to be able to return. Could be avoided with some checking.
} else {
// Delay slot
MOV(R8, gpr.R(rs)); // Save the destination address through the delay slot. Could use isNice to avoid when the jit is fully implemented
MovToPC(R8); // For syscall to be able to return. Could be avoided with some checking.
CompileAt(js.compilerPC + 4);
FlushAll();
if (!js.compiling) {
// INFO_LOG(HLE, "Syscall in delay slot!");
return;
}
}
switch (op & 0x3f)
{
case 8: //jr
break;
case 9: //jalr
ADD(R1, R10, MIPS_REG_RA * 4); // compute address of RA in ram
ARMABI_MOVI2R(R2, js.compilerPC + 8);
STR(R1, R2);
ARMABI_MOVI2R(R0, js.compilerPC + 8);
STR(R1, R0);
break;
default:
_dbg_assert_msg_(CPU,0,"Trying to compile instruction that can't be compiled");
break;
}
WriteExitDestInR(R0);
WriteExitDestInR(R8);
js.compiling = false;
}
@ -388,15 +427,10 @@ void Jit::Comp_Syscall(u32 op)
{
FlushAll();
// By putting mips_ in a register and using offsets, we could get rid of one of the constant-sets.
ARMABI_MOVI2R(R0, (u32)&mips_->r[MIPS_REG_RA]);
LDR(R0, R0);
ARMABI_MOVI2R(R1, (u32)&mips_->pc);
STR(R1, R0);
ARMABI_CallFunctionC((void *)&CallSyscall, op);
WriteSyscallExit();
js.compiling = false;
}
} // namespace Mipscomp

83
Core/MIPS/ARM/ArmJit.cpp
View File

@ -27,6 +27,30 @@
#include "../../ext/disarm.h"
void DisassembleArm(const u8 *data, int size) {
char temp[256];
for (int i = 0; i < size; i += 4) {
const u32 *codePtr = (const u32 *)(data + i);
u32 inst = codePtr[0];
u32 next = (i < size - 4) ? codePtr[1] : 0;
// MAGIC SPECIAL CASE for MOVW/MOVT readability!
if ((inst & 0x0FF00000) == 0x03000000 && (next & 0x0FF00000) == 0x03400000) {
u32 low = ((inst & 0x000F0000) >> 4) | (inst & 0x0FFF);
u32 hi = ((next & 0x000F0000) >> 4) | (next & 0x0FFF);
int reg0 = (inst & 0x0000F000) >> 12;
int reg1 = (next & 0x0000F000) >> 12;
if (reg0 == reg1) {
sprintf(temp, "%08x MOV32? %s, %04x%04x", (u32)inst, ArmRegName(reg0), hi, low);
INFO_LOG(DYNA_REC, "A: %s", temp);
i += 4;
continue;
}
}
ArmDis((u32)codePtr, inst, temp);
INFO_LOG(DYNA_REC, "A: %s", temp);
}
}
namespace MIPSComp
{
@ -62,6 +86,7 @@ void Jit::CompileAt(u32 addr)
void Jit::Compile(u32 em_address)
{
//ERROR_LOG(CPU, "Compile %08x", em_address);
if (GetSpaceLeft() < 0x10000 || blocks.IsFull())
{
ClearCache();
@ -76,37 +101,14 @@ void Jit::RunLoopUntil(u64 globalticks)
{
// TODO: copy globalticks somewhere
((void (*)())asm_.enterCode)();
INFO_LOG(DYNA_REC, "Left asm code");
INFO_LOG(DYNA_REC, "Left asm code like a boss!");
INFO_LOG(DYNA_REC, "or Two!");
}
void Hullo(int a, int b, int c, int d) {
INFO_LOG(DYNA_REC, "Hullo %08x %08x %08x %08x", a, b, c, d);
}
static void DisassembleArm(const u8 *data, int size) {
char temp[256];
for (int i = 0; i < size; i += 4) {
const u32 *codePtr = (const u32 *)(data + i);
u32 inst = codePtr[0];
u32 next = (i < size - 4) ? codePtr[1] : 0;
// MAGIC SPECIAL CASE for MOVW/MOVT readability!
if ((inst & 0x0FF00000) == 0x03000000 && (next & 0x0FF00000) == 0x03400000) {
u32 low = ((inst & 0x000F0000) >> 4) | (inst & 0x0FFF);
u32 hi = ((next & 0x000F0000) >> 4) | (next & 0x0FFF);
int reg0 = (inst & 0x0000F000) >> 12;
int reg1 = (next & 0x0000F000) >> 12;
if (reg0 == reg1) {
sprintf(temp, "%08x MOV32? %s, %04x%04x", (u32)inst, ArmRegName(reg0), hi, low);
INFO_LOG(DYNA_REC, "A: %s", temp);
i += 4;
continue;
}
}
ArmDis((u32)codePtr, inst, temp);
INFO_LOG(DYNA_REC, "A: %s", temp);
}
}
const u8 *Jit::DoJit(u32 em_address, ArmJitBlock *b)
{
js.cancel = false;
@ -122,7 +124,7 @@ const u8 *Jit::DoJit(u32 em_address, ArmJitBlock *b)
SetCC(CC_LT);
ARMABI_MOVI2R(R0, js.blockStart);
MovToPC(R0);
ARMABI_MOVI2R(R0, (u32)asm_.outerLoop);
ARMABI_MOVI2R(R0, (u32)asm_.outerLoop); // downcount hit zero - go advance.
B(R0);
SetCC(CC_AL);
@ -134,7 +136,7 @@ const u8 *Jit::DoJit(u32 em_address, ArmJitBlock *b)
int numInstructions = 0;
int cycles = 0;
#define LOGASM
// #define LOGASM
#ifdef LOGASM
char temp[256];
#endif
@ -162,7 +164,6 @@ const u8 *Jit::DoJit(u32 em_address, ArmJitBlock *b)
#ifdef LOGASM
DisassembleArm(b->checkedEntry, GetCodePtr() - b->checkedEntry);
#endif
AlignCode16();
b->originalSize = numInstructions;
return b->normalEntry;
@ -196,7 +197,7 @@ void Jit::MovToPC(ARMReg r) {
void Jit::DoDownCount()
{
ARMABI_MOVI2R(R0, Mem(&CoreTiming::downcount));
ARMABI_MOVI2R(R0, (u32)&CoreTiming::downcount);
LDR(R1, R0);
if(js.downcountAmount < 255) // We can enlarge this if we used rotations
{
@ -211,14 +212,6 @@ void Jit::DoDownCount()
}
}
void Jit::WriteExitDestInR(ARMReg Reg)
{
MovToPC(Reg);
DoDownCount();
// TODO: shouldn't need an indirect branch here...
ARMABI_MOVI2R(R0, (u32)asm_.dispatcher);
B(R0);
}
void Jit::WriteExit(u32 destination, int exit_num)
{
@ -230,14 +223,11 @@ void Jit::WriteExit(u32 destination, int exit_num)
// Link opportunity!
int block = blocks.GetBlockNumberFromStartAddress(destination);
if (block >= 0 && jo.enableBlocklink)
{
if (block >= 0 && jo.enableBlocklink) {
// It exists! Joy of joy!
B(blocks.GetBlock(block)->checkedEntry);
b->linkStatus[exit_num] = true;
}
else
{
} else {
ARMABI_MOVI2R(R0, destination);
MovToPC(R0);
ARMABI_MOVI2R(R0, (u32)asm_.dispatcher);
@ -245,6 +235,15 @@ void Jit::WriteExit(u32 destination, int exit_num)
}
}
void Jit::WriteExitDestInR(ARMReg Reg)
{
MovToPC(Reg);
DoDownCount();
// TODO: shouldn't need an indirect branch here...
ARMABI_MOVI2R(R0, (u32)asm_.dispatcher);
B(R0);
}
void Jit::WriteSyscallExit()
{
DoDownCount();

2
Core/MIPS/ARM/ArmJitCache.cpp
View File

@ -107,7 +107,7 @@ void ArmJitBlockCache::Clear()
links_to.clear();
block_map.clear();
num_blocks = 0;
memset(blockCodePointers, 0, sizeof(u8*)*MAX_NUM_BLOCKS);
memset(blockCodePointers, 0xCC, sizeof(u8*)*MAX_NUM_BLOCKS);
}
void ArmJitBlockCache::ClearSafe()

1
Core/MIPS/MIPSInt.cpp
View File

@ -272,6 +272,7 @@ namespace MIPSInt
// There's one of these in Star Soldier at 0881808c, which seems benign - it should probably be ignored.
if (op == 0x03e00008)
return;
ERROR_LOG(HLE, "Jump in delay slot :(");
_dbg_assert_msg_(CPU,0,"Jump in delay slot :(");
}

4
Core/MIPS/x86/Asm.cpp
View File

@ -87,7 +87,7 @@ void AsmRoutineManager::Generate(MIPSState *mips, MIPSComp::Jit *jit)
dispatcher = GetCodePtr();
// The result of slice decrementation should be in flags if somebody jumped here
// IMPORTANT - We jump on negative, not carry!!!
FixupBranch bail = J_CC(CC_BE, true);
FixupBranch bail = J_CC(CC_S, true);
SetJumpTarget(skipToRealDispatch);
@ -138,12 +138,10 @@ void AsmRoutineManager::Generate(MIPSState *mips, MIPSComp::Jit *jit)
J_CC(CC_Z, outerLoop, true);
SetJumpTarget(badCoreState);
//Landing pad for drec space
ABI_PopAllCalleeSavedRegsAndAdjustStack();
RET();
breakpointBailout = GetCodePtr();
//Landing pad for drec space
ABI_PopAllCalleeSavedRegsAndAdjustStack();
RET();
}

21
Core/MIPS/x86/Jit.cpp
View File

@ -57,6 +57,7 @@ void Jit::CompileAt(u32 addr)
void Jit::Compile(u32 em_address)
{
ERROR_LOG(CPU, "Compile %08x", em_address);
if (GetSpaceLeft() < 0x10000 || blocks.IsFull())
{
ClearCache();
@ -146,19 +147,15 @@ void Jit::WriteExit(u32 destination, int exit_num)
// Link opportunity!
int block = blocks.GetBlockNumberFromStartAddress(destination);
if (jo.enableBlocklink)
{
if (block >= 0 && jo.enableBlocklink)
{
// It exists! Joy of joy!
JMP(blocks.GetBlock(block)->checkedEntry, true);
b->linkStatus[exit_num] = true;
return;
}
if (block >= 0 && jo.enableBlocklink) {
// It exists! Joy of joy!
JMP(blocks.GetBlock(block)->checkedEntry, true);
b->linkStatus[exit_num] = true;
} else {
// No blocklinking.
MOV(32, M(&mips_->pc), Imm32(destination));
JMP(asm_.dispatcher, true);
}
// No blocklinking.
MOV(32, M(&mips_->pc), Imm32(destination));
JMP(asm_.dispatcher, true);
}
void Jit::WriteExitDestInEAX()

4
android/jni/Android.mk
View File

@ -24,8 +24,8 @@ LOCAL_MODULE := ppsspp_jni
NATIVE := ../../native
SRC := ../..
LOCAL_CFLAGS := -DUSE_PROFILER -DARM -DGL_GLEXT_PROTOTYPES -DUSING_GLES2 -O2 -fsigned-char -Wall -Wno-multichar -Wno-psabi -Wno-unused-variable -fno-strict-aliasing -ffast-math
LOCAL_CPPFLAGS := -std=gnu++0x
LOCAL_CFLAGS := -DUSE_PROFILER -DARM -DGL_GLEXT_PROTOTYPES -DUSING_GLES2 -g -fsigned-char -Wall -Wno-multichar -Wno-psabi -Wno-unused-variable -fno-strict-aliasing -ffast-math
LOCAL_CXXFLAGS := -std=gnu++0x
LOCAL_C_INCLUDES := \
$(LOCAL_PATH)/../../Common \
$(LOCAL_PATH)/../.. \