mirror of
https://github.com/hrydgard/ppsspp.git
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Merge pull request #18006 from unknownbrackets/x86-jit-float
x86jit: A few more ops, float literal pool
This commit is contained in:
Henrik Rydgård
GitHub
commit
8976b0f55c
@ -280,6 +280,9 @@ void X64JitBackend::GenerateFixedCode(MIPSState *mipsState) {
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#endif
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}
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EmitFPUConstants();
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EmitVecConstants();
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// Let's spare the pre-generated code from unprotect-reprotect.
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AlignCodePage();
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jitStartOffset_ = (int)(GetCodePtr() - start);
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@ -40,13 +40,23 @@ namespace MIPSComp {
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using namespace Gen;
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using namespace X64IRJitConstants;
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static struct SimdConstants {
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alignas(16) const u32 reverseQNAN[4] = { 0x803FFFFF, 0x803FFFFF, 0x803FFFFF, 0x803FFFFF };
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alignas(16) const u32 noSignMask[4] = { 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF };
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alignas(16) const u32 positiveInfinity[4] = { 0x7F800000, 0x7F800000, 0x7F800000, 0x7F800000 };
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alignas(16) const u32 signBitAll[4] = { 0x80000000, 0x80000000, 0x80000000, 0x80000000 };
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alignas(16) const u32 ones[4] = { 0x3F800000, 0x3F800000, 0x3F800000, 0x3F800000 };
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} simdConstants;
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void X64JitBackend::EmitFPUConstants() {
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EmitConst4x32(&constants.noSignMask, 0x7FFFFFFF);
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EmitConst4x32(&constants.signBitAll, 0x80000000);
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EmitConst4x32(&constants.positiveInfinity, 0x7F800000);
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EmitConst4x32(&constants.qNAN, 0x7FC00000);
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EmitConst4x32(&constants.positiveOnes, 0x3F800000);
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EmitConst4x32(&constants.negativeOnes, 0xBF800000);
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constants.mulTableVi2f = (const float *)GetCodePointer();
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for (uint8_t i = 0; i < 32; ++i) {
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float fval = 1.0f / (1UL << i);
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uint32_t val;
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memcpy(&val, &fval, sizeof(val));
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Write32(val);
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}
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}
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void X64JitBackend::CompIR_FArith(IRInst inst) {
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CONDITIONAL_DISABLE;
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@ -87,11 +97,11 @@ void X64JitBackend::CompIR_FArith(IRInst inst) {
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case IROp::FMul:
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{
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X64Reg tempReg = regs_.MapWithFPRTemp(inst);
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regs_.Map(inst);
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UCOMISS(regs_.FX(inst.src1), regs_.F(inst.src2));
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SETcc(CC_P, R(SCRATCH1));
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// tempReg = !my_isnan(src1) && !my_isnan(src2)
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MOVSS(tempReg, regs_.F(inst.src1));
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CMPORDSS(tempReg, regs_.F(inst.src2));
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if (inst.dest == inst.src1) {
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MULSS(regs_.FX(inst.dest), regs_.F(inst.src2));
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} else if (inst.dest == inst.src2) {
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@ -103,22 +113,18 @@ void X64JitBackend::CompIR_FArith(IRInst inst) {
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MULSS(regs_.FX(inst.dest), regs_.F(inst.src2));
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}
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// Abuse a lane of tempReg to remember dest: NAN, NAN, res, res.
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SHUFPS(tempReg, regs_.F(inst.dest), 0);
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// dest = my_isnan(dest) && !my_isnan(src1) && !my_isnan(src2)
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CMPUNORDSS(regs_.FX(inst.dest), regs_.F(inst.dest));
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ANDPS(regs_.FX(inst.dest), R(tempReg));
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// At this point fd = FFFFFFFF if non-NAN inputs produced a NAN output.
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// We'll AND it with the inverse QNAN bits to clear (00000000 means no change.)
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if (RipAccessible(&simdConstants.reverseQNAN)) {
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ANDPS(regs_.FX(inst.dest), M(&simdConstants.reverseQNAN)); // rip accessible
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} else {
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MOV(PTRBITS, R(SCRATCH1), ImmPtr(&simdConstants.reverseQNAN));
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ANDPS(regs_.FX(inst.dest), MatR(SCRATCH1));
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}
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// ANDN is backwards, which is why we saved XMM0 to start. Now put it back.
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SHUFPS(tempReg, R(tempReg), 0xFF);
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ANDNPS(regs_.FX(inst.dest), R(tempReg));
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UCOMISS(regs_.FX(inst.dest), regs_.F(inst.dest));
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FixupBranch handleNAN = J_CC(CC_P);
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FixupBranch finish = J();
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SetJumpTarget(handleNAN);
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TEST(8, R(SCRATCH1), R(SCRATCH1));
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FixupBranch keepNAN = J_CC(CC_NZ);
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MOVSS(regs_.FX(inst.dest), M(constants.qNAN)); // rip accessible
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SetJumpTarget(keepNAN);
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SetJumpTarget(finish);
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break;
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}
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@ -149,21 +155,11 @@ void X64JitBackend::CompIR_FArith(IRInst inst) {
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case IROp::FNeg:
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regs_.Map(inst);
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if (cpu_info.bAVX) {
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if (RipAccessible(&simdConstants.signBitAll)) {
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VXORPS(128, regs_.FX(inst.dest), regs_.FX(inst.src1), M(&simdConstants.signBitAll)); // rip accessible
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} else {
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MOV(PTRBITS, R(SCRATCH1), ImmPtr(&simdConstants.signBitAll));
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VXORPS(128, regs_.FX(inst.dest), regs_.FX(inst.src1), MatR(SCRATCH1));
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}
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VXORPS(128, regs_.FX(inst.dest), regs_.FX(inst.src1), M(constants.signBitAll)); // rip accessible
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} else {
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if (inst.dest != inst.src1)
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MOVAPS(regs_.FX(inst.dest), regs_.F(inst.src1));
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if (RipAccessible(&simdConstants.signBitAll)) {
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XORPS(regs_.FX(inst.dest), M(&simdConstants.signBitAll)); // rip accessible
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} else {
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MOV(PTRBITS, R(SCRATCH1), ImmPtr(&simdConstants.signBitAll));
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XORPS(regs_.FX(inst.dest), MatR(SCRATCH1));
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}
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XORPS(regs_.FX(inst.dest), M(constants.signBitAll)); // rip accessible
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}
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break;
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@ -187,21 +183,11 @@ void X64JitBackend::CompIR_FAssign(IRInst inst) {
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case IROp::FAbs:
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regs_.Map(inst);
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if (cpu_info.bAVX) {
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if (RipAccessible(&simdConstants.noSignMask)) {
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VANDPS(128, regs_.FX(inst.dest), regs_.FX(inst.src1), M(&simdConstants.noSignMask)); // rip accessible
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} else {
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MOV(PTRBITS, R(SCRATCH1), ImmPtr(&simdConstants.noSignMask));
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VANDPS(128, regs_.FX(inst.dest), regs_.FX(inst.src1), MatR(SCRATCH1));
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}
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VANDPS(128, regs_.FX(inst.dest), regs_.FX(inst.src1), M(constants.noSignMask)); // rip accessible
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} else {
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if (inst.dest != inst.src1)
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MOVAPS(regs_.FX(inst.dest), regs_.F(inst.src1));
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if (RipAccessible(&simdConstants.noSignMask)) {
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ANDPS(regs_.FX(inst.dest), M(&simdConstants.noSignMask)); // rip accessible
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} else {
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MOV(PTRBITS, R(SCRATCH1), ImmPtr(&simdConstants.noSignMask));
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ANDPS(regs_.FX(inst.dest), MatR(SCRATCH1));
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}
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ANDPS(regs_.FX(inst.dest), M(constants.noSignMask)); // rip accessible
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}
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break;
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@ -388,28 +374,13 @@ void X64JitBackend::CompIR_FCompare(IRInst inst) {
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case VC_EI:
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case VC_NI:
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regs_.MapFPR(inst.src1);
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if (!RipAccessible(&simdConstants.noSignMask) || !RipAccessible(&simdConstants.positiveInfinity)) {
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MOV(PTRBITS, R(SCRATCH1), ImmPtr(&simdConstants));
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}
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if (cpu_info.bAVX) {
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if (RipAccessible(&simdConstants.noSignMask)) {
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VANDPS(128, tempReg, regs_.FX(inst.src1), M(&simdConstants.noSignMask)); // rip accessible
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} else {
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VANDPS(128, tempReg, regs_.FX(inst.src1), MDisp(SCRATCH1, offsetof(SimdConstants, noSignMask)));
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}
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VANDPS(128, tempReg, regs_.FX(inst.src1), M(constants.noSignMask)); // rip accessible
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} else {
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MOVAPS(tempReg, regs_.F(inst.src1));
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if (RipAccessible(&simdConstants.noSignMask)) {
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ANDPS(tempReg, M(&simdConstants.noSignMask)); // rip accessible
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} else {
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ANDPS(tempReg, MDisp(SCRATCH1, offsetof(SimdConstants, noSignMask)));
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}
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}
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if (RipAccessible(&simdConstants.positiveInfinity)) {
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CMPSS(tempReg, M(&simdConstants.positiveInfinity), !condNegated ? CMP_EQ : CMP_LT); // rip accessible
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} else {
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CMPSS(tempReg, MDisp(SCRATCH1, offsetof(SimdConstants, positiveInfinity)), !condNegated ? CMP_EQ : CMP_LT);
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ANDPS(tempReg, M(constants.noSignMask)); // rip accessible
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}
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CMPSS(tempReg, M(constants.positiveInfinity), !condNegated ? CMP_EQ : CMP_LT); // rip accessible
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break;
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case VC_ES:
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case VC_NS:
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@ -571,10 +542,15 @@ void X64JitBackend::CompIR_FCvt(IRInst inst) {
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break;
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case IROp::FCvtScaledWS:
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case IROp::FCvtScaledSW:
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CompIR_Generic(inst);
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break;
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case IROp::FCvtScaledSW:
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regs_.Map(inst);
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CVTDQ2PS(regs_.FX(inst.dest), regs_.F(inst.src1));
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MULSS(regs_.FX(inst.dest), M(&constants.mulTableVi2f[inst.src2 & 0x1F])); // rip accessible
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break;
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default:
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INVALIDOP;
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break;
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@ -635,10 +611,37 @@ void X64JitBackend::CompIR_FRound(IRInst inst) {
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void X64JitBackend::CompIR_FSat(IRInst inst) {
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CONDITIONAL_DISABLE;
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X64Reg tempReg = INVALID_REG;
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switch (inst.op) {
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case IROp::FSat0_1:
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tempReg = regs_.MapWithFPRTemp(inst);
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// The second argument's NAN is taken if either is NAN, so put known first.
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MOVSS(tempReg, M(constants.positiveOnes));
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MINSS(tempReg, regs_.F(inst.src1));
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// Now for NAN, we want known first again.
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// Unfortunately, this will retain -0.0, which we'll fix next.
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XORPS(tempReg, R(tempReg));
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MAXSS(tempReg, regs_.F(inst.dest));
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// Important: this should clamp -0.0 to +0.0.
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XORPS(regs_.FX(inst.dest), regs_.F(inst.dest));
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CMPEQSS(regs_.FX(inst.dest), R(tempReg));
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// This will zero all bits if it was -0.0, and keep them otherwise.
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ANDNPS(regs_.FX(inst.dest), R(tempReg));
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break;
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case IROp::FSatMinus1_1:
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CompIR_Generic(inst);
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tempReg = regs_.MapWithFPRTemp(inst);
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// The second argument's NAN is taken if either is NAN, so put known first.
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MOVSS(tempReg, M(constants.negativeOnes));
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MAXSS(tempReg, regs_.F(inst.src1));
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// Again, stick with the first argument being known.
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MOVSS(regs_.FX(inst.dest), M(constants.positiveOnes));
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MINSS(regs_.FX(inst.dest), R(tempReg));
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break;
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default:
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@ -756,12 +759,7 @@ void X64JitBackend::CompIR_FSpecial(IRInst inst) {
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X64Reg tempReg = regs_.MapWithFPRTemp(inst);
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SQRTSS(tempReg, regs_.F(inst.src1));
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if (RipAccessible(&simdConstants.ones)) {
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MOVSS(regs_.FX(inst.dest), M(&simdConstants.ones)); // rip accessible
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} else {
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MOV(PTRBITS, R(SCRATCH1), ImmPtr(&simdConstants.ones));
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MOVSS(regs_.FX(inst.dest), MatR(SCRATCH1));
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}
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MOVSS(regs_.FX(inst.dest), M(constants.positiveOnes)); // rip accessible
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DIVSS(regs_.FX(inst.dest), R(tempReg));
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break;
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}
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@ -769,21 +767,11 @@ void X64JitBackend::CompIR_FSpecial(IRInst inst) {
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case IROp::FRecip:
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if (inst.dest != inst.src1) {
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regs_.Map(inst);
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if (RipAccessible(&simdConstants.ones)) {
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MOVSS(regs_.FX(inst.dest), M(&simdConstants.ones)); // rip accessible
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} else {
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MOV(PTRBITS, R(SCRATCH1), ImmPtr(&simdConstants.ones));
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MOVSS(regs_.FX(inst.dest), MatR(SCRATCH1));
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}
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MOVSS(regs_.FX(inst.dest), M(constants.positiveOnes)); // rip accessible
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DIVSS(regs_.FX(inst.dest), regs_.F(inst.src1));
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} else {
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X64Reg tempReg = regs_.MapWithFPRTemp(inst);
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if (RipAccessible(&simdConstants.ones)) {
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MOVSS(tempReg, M(&simdConstants.ones)); // rip accessible
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} else {
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MOV(PTRBITS, R(SCRATCH1), ImmPtr(&simdConstants.ones));
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MOVSS(tempReg, MatR(SCRATCH1));
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}
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MOVSS(tempReg, M(constants.positiveOnes)); // rip accessible
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if (cpu_info.bAVX) {
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VDIVSS(regs_.FX(inst.dest), tempReg, regs_.F(inst.src1));
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} else {
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@ -39,25 +39,31 @@ namespace MIPSComp {
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using namespace Gen;
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using namespace X64IRJitConstants;
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static struct SimdConstants {
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alignas(16) const u32 noSignMask[4] = { 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF };
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alignas(16) const u32 signBitAll[4] = { 0x80000000, 0x80000000, 0x80000000, 0x80000000 };
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} simdConstants;
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alignas(16) static const float vec4InitValues[8][4] = {
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{ 0.0f, 0.0f, 0.0f, 0.0f },
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{ 1.0f, 1.0f, 1.0f, 1.0f },
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{ -1.0f, -1.0f, -1.0f, -1.0f },
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{ 1.0f, 0.0f, 0.0f, 0.0f },
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{ 0.0f, 1.0f, 0.0f, 0.0f },
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{ 0.0f, 0.0f, 1.0f, 0.0f },
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{ 0.0f, 0.0f, 0.0f, 1.0f },
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};
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static bool Overlap(IRReg r1, int l1, IRReg r2, int l2) {
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return r1 < r2 + l2 && r1 + l1 > r2;
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}
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void X64JitBackend::EmitVecConstants() {
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static const float vec4InitData[8][4] = {
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{ 0.0f, 0.0f, 0.0f, 0.0f },
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{ 1.0f, 1.0f, 1.0f, 1.0f },
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{ -1.0f, -1.0f, -1.0f, -1.0f },
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{ 1.0f, 0.0f, 0.0f, 0.0f },
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{ 0.0f, 1.0f, 0.0f, 0.0f },
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{ 0.0f, 0.0f, 1.0f, 0.0f },
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{ 0.0f, 0.0f, 0.0f, 1.0f },
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};
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constants.vec4InitValues = (const Float4Constant *)GetCodePointer();
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for (size_t type = 0; type < ARRAY_SIZE(vec4InitData); ++type) {
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for (int i = 0; i < 4; ++i) {
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uint32_t val;
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memcpy(&val, &vec4InitData[type][i], sizeof(val));
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Write32(val);
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}
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}
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}
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void X64JitBackend::CompIR_VecArith(IRInst inst) {
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CONDITIONAL_DISABLE;
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@ -150,42 +156,22 @@ void X64JitBackend::CompIR_VecArith(IRInst inst) {
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case IROp::Vec4Neg:
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regs_.Map(inst);
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if (cpu_info.bAVX) {
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if (RipAccessible(&simdConstants.signBitAll)) {
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VXORPS(128, regs_.FX(inst.dest), regs_.FX(inst.src1), M(&simdConstants.signBitAll)); // rip accessible
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} else {
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MOV(PTRBITS, R(SCRATCH1), ImmPtr(&simdConstants.signBitAll));
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VXORPS(128, regs_.FX(inst.dest), regs_.FX(inst.src1), MatR(SCRATCH1));
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}
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VXORPS(128, regs_.FX(inst.dest), regs_.FX(inst.src1), M(constants.signBitAll)); // rip accessible
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} else {
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if (inst.dest != inst.src1)
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MOVAPS(regs_.FX(inst.dest), regs_.F(inst.src1));
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if (RipAccessible(&simdConstants.signBitAll)) {
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XORPS(regs_.FX(inst.dest), M(&simdConstants.signBitAll)); // rip accessible
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} else {
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MOV(PTRBITS, R(SCRATCH1), ImmPtr(&simdConstants.signBitAll));
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XORPS(regs_.FX(inst.dest), MatR(SCRATCH1));
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}
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XORPS(regs_.FX(inst.dest), M(constants.signBitAll)); // rip accessible
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}
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break;
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case IROp::Vec4Abs:
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regs_.Map(inst);
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if (cpu_info.bAVX) {
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if (RipAccessible(&simdConstants.noSignMask)) {
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VANDPS(128, regs_.FX(inst.dest), regs_.FX(inst.src1), M(&simdConstants.noSignMask)); // rip accessible
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} else {
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MOV(PTRBITS, R(SCRATCH1), ImmPtr(&simdConstants.noSignMask));
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VANDPS(128, regs_.FX(inst.dest), regs_.FX(inst.src1), MatR(SCRATCH1));
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}
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VANDPS(128, regs_.FX(inst.dest), regs_.FX(inst.src1), M(constants.noSignMask)); // rip accessible
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} else {
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if (inst.dest != inst.src1)
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MOVAPS(regs_.FX(inst.dest), regs_.F(inst.src1));
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if (RipAccessible(&simdConstants.noSignMask)) {
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ANDPS(regs_.FX(inst.dest), M(&simdConstants.noSignMask)); // rip accessible
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} else {
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MOV(PTRBITS, R(SCRATCH1), ImmPtr(&simdConstants.noSignMask));
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ANDPS(regs_.FX(inst.dest), MatR(SCRATCH1));
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}
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ANDPS(regs_.FX(inst.dest), M(constants.noSignMask)); // rip accessible
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}
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break;
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@ -203,11 +189,8 @@ void X64JitBackend::CompIR_VecAssign(IRInst inst) {
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regs_.Map(inst);
|
||||
if (inst.src1 == (int)Vec4Init::AllZERO) {
|
||||
XORPS(regs_.FX(inst.dest), regs_.F(inst.dest));
|
||||
} else if (RipAccessible(&vec4InitValues[inst.src1])) {
|
||||
MOVAPS(regs_.FX(inst.dest), M(&vec4InitValues[inst.src1])); // rip accessible
|
||||
} else {
|
||||
MOV(PTRBITS, R(SCRATCH1), ImmPtr(&vec4InitValues[inst.src1]));
|
||||
MOVAPS(regs_.FX(inst.dest), MatR(SCRATCH1));
|
||||
} else {
|
||||
MOVAPS(regs_.FX(inst.dest), M(&constants.vec4InitValues[inst.src1])); // rip accessible
|
||||
}
|
||||
break;
|
||||
|
||||
|
||||
@ -337,6 +337,12 @@ void X64JitBackend::LoadStaticRegisters() {
|
||||
}
|
||||
}
|
||||
|
||||
void X64JitBackend::EmitConst4x32(const void **c, uint32_t v) {
|
||||
*c = AlignCode16();
|
||||
for (int i = 0; i < 4; ++i)
|
||||
Write32(v);
|
||||
}
|
||||
|
||||
} // namespace MIPSComp
|
||||
|
||||
#endif
|
||||
|
||||
@ -119,6 +119,10 @@ private:
|
||||
void CompIR_VecStore(IRInst inst) override;
|
||||
void CompIR_ValidateAddress(IRInst inst) override;
|
||||
|
||||
void EmitConst4x32(const void **c, uint32_t v);
|
||||
void EmitFPUConstants();
|
||||
void EmitVecConstants();
|
||||
|
||||
Gen::OpArg PrepareSrc1Address(IRInst inst);
|
||||
|
||||
JitOptions &jo;
|
||||
@ -135,6 +139,19 @@ private:
|
||||
const u8 *saveStaticRegisters_ = nullptr;
|
||||
const u8 *loadStaticRegisters_ = nullptr;
|
||||
|
||||
typedef struct { float f[4]; } Float4Constant;
|
||||
struct Constants {
|
||||
const void *noSignMask;
|
||||
const void *signBitAll;
|
||||
const void *positiveInfinity;
|
||||
const void *positiveOnes;
|
||||
const void *negativeOnes;
|
||||
const void *qNAN;
|
||||
const float *mulTableVi2f;
|
||||
const Float4Constant *vec4InitValues;
|
||||
};
|
||||
Constants constants;
|
||||
|
||||
int jitStartOffset_ = 0;
|
||||
int compilingBlockNum_ = -1;
|
||||
int logBlocks_ = 0;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user