riscv: Add debug log of block disasm.

This commit is contained in:
Unknown W. Brackets 2023-08-13 09:28:06 -07:00
parent 81f67c717c
commit 8c036a889d

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@ -15,6 +15,8 @@
// Official git repository and contact information can be found at
// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
#include <cstddef>
#include "ext/riscv-disas.h"
#include "Core/MemMap.h"
#include "Core/MIPS/MIPSTables.h"
#include "Core/MIPS/RiscV/RiscVJit.h"
@ -29,6 +31,9 @@ using namespace RiscVJitConstants;
static constexpr int MIN_BLOCK_NORMAL_LEN = 16;
static constexpr int MIN_BLOCK_EXIT_LEN = 8;
// Use this if you want to check a specific block (correlates IR) or -1 for all.
static constexpr uint32_t disasmBlockAddr = 0;
RiscVJitBackend::RiscVJitBackend(MIPSState *mipsState, JitOptions &jitopt, IRBlockCache &blocks)
: IRNativeBackend(blocks), jo(jitopt), gpr(mipsState, &jo), fpr(mipsState, &jo) {
// Automatically disable incompatible options.
@ -77,10 +82,15 @@ bool RiscVJitBackend::CompileBlock(IRBlock *block, int block_num, bool preload)
gpr.Start(block);
fpr.Start(block);
// Used only for disasmBlockAddr.
std::map<const u8 *, IRInst> addresses;
for (int i = 0; i < block->GetNumInstructions(); ++i) {
const IRInst &inst = block->GetInstructions()[i];
gpr.SetIRIndex(i);
fpr.SetIRIndex(i);
if constexpr (disasmBlockAddr != 0) {
addresses[GetCodePtr()] = inst;
}
CompileIRInst(inst);
@ -127,6 +137,28 @@ bool RiscVJitBackend::CompileBlock(IRBlock *block, int block_num, bool preload)
QuickJ(R_RA, outerLoopPCInSCRATCH1_);
}
if (disasmBlockAddr == -1 || disasmBlockAddr == startPC) {
INFO_LOG(JIT, "== RISCV ==");
INFO_LOG(JIT, "=============== RISCV (%d bytes) ===============", len);
for (const u8 *p = blockStart; p < GetCodePointer(); ) {
char temp[512];
rv_inst inst;
size_t len;
auto it = addresses.find(p);
if (it != addresses.end()) {
DisassembleIR(temp, sizeof(temp), it->second);
INFO_LOG(JIT, "IR: # %s", temp);
}
riscv_inst_fetch(p, &inst, &len);
riscv_disasm_inst(temp, sizeof(temp), rv64, (uintptr_t)p, inst);
p += len;
INFO_LOG(JIT, "RV: %s", temp);
}
}
FlushIcache();
compilingBlockNum_ = -1;