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riscv: Add debug log of block disasm.
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@ -15,6 +15,8 @@
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include <cstddef>
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#include "ext/riscv-disas.h"
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#include "Core/MemMap.h"
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#include "Core/MIPS/MIPSTables.h"
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#include "Core/MIPS/RiscV/RiscVJit.h"
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@ -29,6 +31,9 @@ using namespace RiscVJitConstants;
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static constexpr int MIN_BLOCK_NORMAL_LEN = 16;
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static constexpr int MIN_BLOCK_EXIT_LEN = 8;
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// Use this if you want to check a specific block (correlates IR) or -1 for all.
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static constexpr uint32_t disasmBlockAddr = 0;
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RiscVJitBackend::RiscVJitBackend(MIPSState *mipsState, JitOptions &jitopt, IRBlockCache &blocks)
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: IRNativeBackend(blocks), jo(jitopt), gpr(mipsState, &jo), fpr(mipsState, &jo) {
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// Automatically disable incompatible options.
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@ -77,10 +82,15 @@ bool RiscVJitBackend::CompileBlock(IRBlock *block, int block_num, bool preload)
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gpr.Start(block);
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fpr.Start(block);
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// Used only for disasmBlockAddr.
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std::map<const u8 *, IRInst> addresses;
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for (int i = 0; i < block->GetNumInstructions(); ++i) {
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const IRInst &inst = block->GetInstructions()[i];
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gpr.SetIRIndex(i);
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fpr.SetIRIndex(i);
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if constexpr (disasmBlockAddr != 0) {
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addresses[GetCodePtr()] = inst;
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}
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CompileIRInst(inst);
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@ -127,6 +137,28 @@ bool RiscVJitBackend::CompileBlock(IRBlock *block, int block_num, bool preload)
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QuickJ(R_RA, outerLoopPCInSCRATCH1_);
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}
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if (disasmBlockAddr == -1 || disasmBlockAddr == startPC) {
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INFO_LOG(JIT, "== RISCV ==");
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INFO_LOG(JIT, "=============== RISCV (%d bytes) ===============", len);
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for (const u8 *p = blockStart; p < GetCodePointer(); ) {
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char temp[512];
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rv_inst inst;
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size_t len;
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auto it = addresses.find(p);
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if (it != addresses.end()) {
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DisassembleIR(temp, sizeof(temp), it->second);
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INFO_LOG(JIT, "IR: # %s", temp);
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}
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riscv_inst_fetch(p, &inst, &len);
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riscv_disasm_inst(temp, sizeof(temp), rv64, (uintptr_t)p, inst);
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p += len;
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INFO_LOG(JIT, "RV: %s", temp);
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}
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}
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FlushIcache();
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compilingBlockNum_ = -1;
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