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riscv: Implement vi2s.

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This commit is contained in:
Unknown W. Brackets 2023-07-29 07:50:06 -07:00
parent e2765db4dc
commit 921bd2391c
1 changed files with 16 additions and 1 deletions
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17
Core/MIPS/RiscV/RiscVCompVec.cpp
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@ -241,10 +241,25 @@ void RiscVJit::CompIR_VecPack(IRInst inst) {
case IROp::Vec4Pack31To8:
case IROp::Vec4Pack32To8:
case IROp::Vec2Pack31To16:
case IROp::Vec2Pack32To16:
CompIR_Generic(inst);
break;
case IROp::Vec2Pack32To16:
fpr.MapDirtyInIn(inst.dest, inst.src1, inst.src1 + 1);
FMV(FMv::X, FMv::W, SCRATCH1, fpr.R(inst.src1));
FMV(FMv::X, FMv::W, SCRATCH2, fpr.R(inst.src1 + 1));
// Keep in mind, this was sign-extended, so we have to zero the upper.
SLLI(SCRATCH1, SCRATCH1, XLEN - 32);
// Now we just set (SCRATCH2 & 0xFFFF0000) | SCRATCH1.
SRLI(SCRATCH1, SCRATCH1, XLEN - 16);
// Use a wall to mask. We can ignore the upper 32 here.
SRLI(SCRATCH2, SCRATCH2, 16);
SLLI(SCRATCH2, SCRATCH2, 16);
OR(SCRATCH1, SCRATCH1, SCRATCH2);
// Okay, to the floating point register.
FMV(FMv::W, FMv::X, fpr.R(inst.dest), SCRATCH1);
break;
default:
INVALIDOP;
break;