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x86jit: Implement ll/sc.

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The point here is that breakpoints now work for ll and sc.
This commit is contained in:
Unknown W. Brackets 2023-07-29 18:49:45 -07:00
parent f0d4267c5e
commit 9a8ac1fe08
1 changed files with 32 additions and 1 deletions
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33
Core/MIPS/x86/CompLoadStore.cpp
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@ -44,6 +44,7 @@
// #define CONDITIONAL_DISABLE(flag) { Comp_Generic(op); return; }
#define CONDITIONAL_DISABLE(flag) if (jo.Disabled(JitDisable::flag)) { Comp_Generic(op); return; }
#define DISABLE { Comp_Generic(op); return; }
#define INVALIDOP { Comp_Generic(op); return; }
namespace MIPSComp {
using namespace Gen;
@ -408,7 +409,37 @@ namespace MIPSComp {
void Jit::Comp_StoreSync(MIPSOpcode op) {
CONDITIONAL_DISABLE(LSU);
DISABLE;
int offset = _IMM16;
MIPSGPReg rt = _RT;
MIPSGPReg rs = _RS;
// Note: still does something even if loading to zero.
CheckMemoryBreakpoint(0, rs, offset);
FixupBranch skipStore;
FixupBranch finish;
switch (op >> 26) {
case 48: // ll
CompITypeMemRead(op, 32, &XEmitter::MOVZX, safeMemFuncs.readU32);
MOV(8, MDisp(X64JitConstants::CTXREG, -128 + offsetof(MIPSState, llBit)), Imm8(1));
break;
case 56: // sc
CMP(8, MDisp(X64JitConstants::CTXREG, -128 + offsetof(MIPSState, llBit)), Imm8(1));
skipStore = J_CC(CC_NE);
CompITypeMemWrite(op, 32, safeMemFuncs.writeU32);
MOV(32, gpr.R(rt), Imm32(1));
finish = J();
SetJumpTarget(skipStore);
MOV(32, gpr.R(rt), Imm32(0));
SetJumpTarget(finish);
break;
default:
INVALIDOP;
}
}
void Jit::Comp_Cache(MIPSOpcode op) {