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https://github.com/hrydgard/ppsspp.git
synced 2025-02-12 17:48:43 +00:00
ARM64: Stub vertex decoder jit, implementing just enough for the cube.elf cube.
This commit is contained in:
Henrik Rydgard
parent
d5faf8b97a
commit
a12e448fb4
@ -265,7 +265,7 @@ static int DefaultNumWorkers() {
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static bool DefaultJit() {
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#ifdef IOS
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return iosCanUseJit;
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#elif defined(ARM) || defined(_M_IX86) || defined(_M_X64)
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#elif defined(ARM) || defined(ARM64) || defined(_M_IX86) || defined(_M_X64)
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return true;
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#else
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return false;
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@ -600,7 +600,7 @@ void ArmJit::RestoreRoundingMode(bool force) {
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}
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void ArmJit::ApplyRoundingMode(bool force) {
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// NOTE: Must not destory R0.
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// NOTE: Must not destroy R0.
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// If the game has never set an interesting rounding mode, we can safely skip this.
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if (g_Config.bSetRoundingMode && (force || !g_Config.bForceFlushToZero || js.hasSetRounding)) {
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LDR(SCRATCHREG2, CTXREG, offsetof(MIPSState, fcr31));
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@ -205,12 +205,10 @@ void Arm64Jit::GenerateFixedCode() {
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FlushIcache();
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if (false) {
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INFO_LOG(JIT, "THE DISASM : %p ========================", enterCode);
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std::vector<std::string> lines = DisassembleArm64(enterCode, GetCodePtr() - enterCode);
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for (auto s : lines) {
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INFO_LOG(JIT, "%s", s.c_str());
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}
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INFO_LOG(JIT, "END OF THE DISASM : %p ========================", GetCodePtr());
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}
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}
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@ -86,8 +86,7 @@ namespace MIPSComp
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DISABLE;
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}
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void Arm64Jit::Comp_VVectorInit(MIPSOpcode op)
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{
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void Arm64Jit::Comp_VVectorInit(MIPSOpcode op) {
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DISABLE;
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}
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@ -95,8 +94,7 @@ namespace MIPSComp
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DISABLE;
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}
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void Arm64Jit::Comp_VMatrixInit(MIPSOpcode op)
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{
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void Arm64Jit::Comp_VMatrixInit(MIPSOpcode op) {
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DISABLE;
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}
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@ -208,7 +206,6 @@ namespace MIPSComp
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// Very heavily used by FF:CC. Should be replaced by a fast approximation instead of
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// calling the math library.
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// Apparently this may not work on hardfp. I don't think we have any platforms using this though.
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void Arm64Jit::Comp_VRot(MIPSOpcode op) {
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DISABLE;
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}
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@ -185,7 +185,7 @@ static void BranchExceptionAndSystem(uint32_t w, uint64_t addr, Instruction *ins
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const char *opname[2] = { "cbz", "cbnz" };
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char r = ((w >> 31) & 1) ? 'x' : 'w';
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int offset = SignExtend19(w >> 5);
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snprintf(instr->text, sizeof(instr->text), "%s %c%d", op, r, Rt);
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snprintf(instr->text, sizeof(instr->text), "%s %c%d", opname[op], r, Rt);
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} else if (((w >> 25) & 0x3F) == 0x1B) {
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// Test and branch
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snprintf(instr->text, sizeof(instr->text), "(test & branch %08x)", w);
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@ -1174,7 +1174,6 @@ void VertexDecoderJitCache::Jit_PosS16Through() {
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_dbg_assert_msg_(JIT, fpScratchReg + 1 == fpScratchReg2, "VertexDecoder fpScratchRegs must be in order.");
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_dbg_assert_msg_(JIT, fpScratchReg2 + 1 == fpScratchReg3, "VertexDecoder fpScratchRegs must be in order.");
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// TODO: SIMD
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LDRSH(tempReg1, srcReg, dec_->posoff);
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LDRSH(tempReg2, srcReg, dec_->posoff + 2);
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LDRH(tempReg3, srcReg, dec_->posoff + 4);
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@ -20,14 +20,239 @@
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#include "Core/Config.h"
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#include "Core/Reporting.h"
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#include "Common/Arm64Emitter.h"
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#include "Core/MIPS/JitCommon/JitCommon.h"
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#include "GPU/GPUState.h"
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#include "GPU/Common/VertexDecoderCommon.h"
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static const float by128 = 1.0f / 128.0f;
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static const float by16384 = 1.0f / 16384.0f;
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static const float by32768 = 1.0f / 32768.0f;
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using namespace Arm64Gen;
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// Pointers, X regs
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static const ARM64Reg srcReg = X0;
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static const ARM64Reg dstReg = X1;
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static const ARM64Reg counterReg = W2;
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static const ARM64Reg tempReg1 = W3;
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static const ARM64Reg tempReg2 = W4;
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static const ARM64Reg tempReg3 = W5;
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static const ARM64Reg scratchReg = W6;
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static const ARM64Reg scratchReg2 = W7;
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static const ARM64Reg scratchReg3 = W8;
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static const ARM64Reg fullAlphaReg = W12;
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static const ARM64Reg fpScratchReg = S4;
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static const ARM64Reg fpScratchReg2 = S5;
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static const ARM64Reg fpScratchReg3 = S6;
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static const ARM64Reg fpScratchReg4 = S7;
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static const ARM64Reg fpUVscaleReg = D0;
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static const ARM64Reg fpUVoffsetReg = D1;
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static const ARM64Reg neonScratchReg = D2;
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static const ARM64Reg neonScratchReg2 = D3;
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static const ARM64Reg neonScratchRegQ = Q1; // Overlaps with all the scratch regs
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// Everything above S6 is fair game for skinning
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// S8-S15 are used during matrix generation
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// These only live through the matrix multiplication
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static const ARM64Reg src[3] = { S8, S9, S10 }; // skin source
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static const ARM64Reg acc[3] = { S11, S12, S13 }; // skin accumulator
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static const ARM64Reg srcNEON = Q2;
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static const ARM64Reg accNEON = Q3;
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static const JitLookup jitLookup[] = {
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/*
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{&VertexDecoder::Step_WeightsU8, &VertexDecoderJitCache::Jit_WeightsU8},
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{&VertexDecoder::Step_WeightsU16, &VertexDecoderJitCache::Jit_WeightsU16},
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{&VertexDecoder::Step_WeightsFloat, &VertexDecoderJitCache::Jit_WeightsFloat},
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{&VertexDecoder::Step_WeightsU8Skin, &VertexDecoderJitCache::Jit_WeightsU8Skin},
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{&VertexDecoder::Step_WeightsU16Skin, &VertexDecoderJitCache::Jit_WeightsU16Skin},
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{&VertexDecoder::Step_WeightsFloatSkin, &VertexDecoderJitCache::Jit_WeightsFloatSkin},
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*/
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{&VertexDecoder::Step_TcU8, &VertexDecoderJitCache::Jit_TcU8},
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{&VertexDecoder::Step_TcU16, &VertexDecoderJitCache::Jit_TcU16},
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{&VertexDecoder::Step_TcFloat, &VertexDecoderJitCache::Jit_TcFloat},
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/*
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{&VertexDecoder::Step_TcU16Double, &VertexDecoderJitCache::Jit_TcU16Double},
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{&VertexDecoder::Step_TcU8Prescale, &VertexDecoderJitCache::Jit_TcU8Prescale},
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{&VertexDecoder::Step_TcU16Prescale, &VertexDecoderJitCache::Jit_TcU16Prescale},
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{&VertexDecoder::Step_TcFloatPrescale, &VertexDecoderJitCache::Jit_TcFloatPrescale},
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{&VertexDecoder::Step_TcU16Through, &VertexDecoderJitCache::Jit_TcU16Through},
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{&VertexDecoder::Step_TcFloatThrough, &VertexDecoderJitCache::Jit_TcFloatThrough},
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{&VertexDecoder::Step_TcU16ThroughDouble, &VertexDecoderJitCache::Jit_TcU16ThroughDouble},
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{&VertexDecoder::Step_NormalS8, &VertexDecoderJitCache::Jit_NormalS8},
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{&VertexDecoder::Step_NormalS16, &VertexDecoderJitCache::Jit_NormalS16},
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{&VertexDecoder::Step_NormalFloat, &VertexDecoderJitCache::Jit_NormalFloat},
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{&VertexDecoder::Step_NormalS8Skin, &VertexDecoderJitCache::Jit_NormalS8Skin},
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{&VertexDecoder::Step_NormalS16Skin, &VertexDecoderJitCache::Jit_NormalS16Skin},
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{&VertexDecoder::Step_NormalFloatSkin, &VertexDecoderJitCache::Jit_NormalFloatSkin},
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*/
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{&VertexDecoder::Step_Color8888, &VertexDecoderJitCache::Jit_Color8888},
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/*
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{&VertexDecoder::Step_Color4444, &VertexDecoderJitCache::Jit_Color4444},
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{&VertexDecoder::Step_Color565, &VertexDecoderJitCache::Jit_Color565},
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{&VertexDecoder::Step_Color5551, &VertexDecoderJitCache::Jit_Color5551},
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{&VertexDecoder::Step_PosS8Through, &VertexDecoderJitCache::Jit_PosS8Through},
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{&VertexDecoder::Step_PosS16Through, &VertexDecoderJitCache::Jit_PosS16Through},
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{&VertexDecoder::Step_PosFloatThrough, &VertexDecoderJitCache::Jit_PosFloat},
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*/
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{&VertexDecoder::Step_PosFloat, &VertexDecoderJitCache::Jit_PosFloat},
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/*
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{&VertexDecoder::Step_PosS8Skin, &VertexDecoderJitCache::Jit_PosS8Skin},
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{&VertexDecoder::Step_PosS16Skin, &VertexDecoderJitCache::Jit_PosS16Skin},
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{&VertexDecoder::Step_PosFloatSkin, &VertexDecoderJitCache::Jit_PosFloatSkin},
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{&VertexDecoder::Step_NormalS8Morph, &VertexDecoderJitCache::Jit_NormalS8Morph},
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{&VertexDecoder::Step_NormalS16Morph, &VertexDecoderJitCache::Jit_NormalS16Morph},
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{&VertexDecoder::Step_NormalFloatMorph, &VertexDecoderJitCache::Jit_NormalFloatMorph},
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{&VertexDecoder::Step_PosS8Morph, &VertexDecoderJitCache::Jit_PosS8Morph},
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{&VertexDecoder::Step_PosS16Morph, &VertexDecoderJitCache::Jit_PosS16Morph},
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{&VertexDecoder::Step_PosFloatMorph, &VertexDecoderJitCache::Jit_PosFloatMorph},
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{&VertexDecoder::Step_Color8888Morph, &VertexDecoderJitCache::Jit_Color8888Morph},
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{&VertexDecoder::Step_Color4444Morph, &VertexDecoderJitCache::Jit_Color4444Morph},
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{&VertexDecoder::Step_Color565Morph, &VertexDecoderJitCache::Jit_Color565Morph},
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{&VertexDecoder::Step_Color5551Morph, &VertexDecoderJitCache::Jit_Color5551Morph},
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*/
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};
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JittedVertexDecoder VertexDecoderJitCache::Compile(const VertexDecoder &dec) {
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// TODO ARM64
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return NULL;
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dec_ = &dec;
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const u8 *start = AlignCode16();
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WARN_LOG(HLE, "VertexDecoderJitCache::Compile");
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bool prescaleStep = false;
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bool skinning = false;
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// Look for prescaled texcoord steps
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for (int i = 0; i < dec.numSteps_; i++) {
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if (dec.steps_[i] == &VertexDecoder::Step_TcU8Prescale ||
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dec.steps_[i] == &VertexDecoder::Step_TcU16Prescale ||
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dec.steps_[i] == &VertexDecoder::Step_TcFloatPrescale) {
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prescaleStep = true;
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}
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if (dec.steps_[i] == &VertexDecoder::Step_WeightsU8Skin ||
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dec.steps_[i] == &VertexDecoder::Step_WeightsU16Skin ||
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dec.steps_[i] == &VertexDecoder::Step_WeightsFloatSkin) {
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skinning = true;
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}
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}
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if (dec.weighttype && g_Config.bSoftwareSkinning && dec.morphcount == 1) {
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WARN_LOG(HLE, "vtxdec-arm64 does not support sw skinning");
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return NULL;
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}
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if (dec.col) {
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// Or LDB and skip the conditional? This is probably cheaper.
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MOVI2R(fullAlphaReg, 0xFF);
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}
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const u8 *loopStart = GetCodePtr();
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for (int i = 0; i < dec.numSteps_; i++) {
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if (!CompileStep(dec, i)) {
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// Reset the code ptr (effectively undoing what we generated) and return zero to indicate that we failed.
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SetCodePtr(const_cast<u8 *>(start));
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char temp[1024] = {0};
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dec.ToString(temp);
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WARN_LOG(HLE, "Could not compile vertex decoder, failed at step %d: %s", i, temp);
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return 0;
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}
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}
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ADDI2R(srcReg, srcReg, dec.VertexSize(), scratchReg);
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ADDI2R(dstReg, dstReg, dec.decFmt.stride, scratchReg);
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SUBS(counterReg, counterReg, 1);
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B(CC_NEQ, loopStart);
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if (dec.col) {
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MOVP2R(tempReg1, &gstate_c.vertexFullAlpha);
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CMP(fullAlphaReg, 0);
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FixupBranch skip = B(CC_NEQ);
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STRB(INDEX_UNSIGNED, fullAlphaReg, tempReg1, 0);
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SetJumpTarget(skip);
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}
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// POP(6, R4, R5, R6, R7, R8, R_PC);
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RET();
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FlushIcache();
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char temp[1024] = { 0 };
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dec.ToString(temp);
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INFO_LOG(HLE, "=== %s (%d bytes) ===", temp, (int)(GetCodePtr() - start));
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std::vector<std::string> lines = DisassembleArm64(start, GetCodePtr() - start);
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for (auto line : lines) {
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INFO_LOG(HLE, "%s", line.c_str());
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}
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INFO_LOG(HLE, "==========", temp);
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return (JittedVertexDecoder)start;
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}
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bool VertexDecoderJitCache::CompileStep(const VertexDecoder &dec, int step) {
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// See if we find a matching JIT function
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for (size_t i = 0; i < ARRAY_SIZE(jitLookup); i++) {
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if (dec.steps_[step] == jitLookup[i].func) {
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((*this).*jitLookup[i].jitFunc)();
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return true;
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}
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}
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return false;
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}
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void VertexDecoderJitCache::Jit_Color8888() {
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LDR(INDEX_UNSIGNED, tempReg1, srcReg, dec_->coloff);
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// TODO: Set flags to determine if alpha != 0xFF.
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// ANDSI2R(tempReg2, tempReg1, 0xFF000000);
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STR(INDEX_UNSIGNED, tempReg1, dstReg, dec_->decFmt.c0off);
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// FixupBranch skip = B(CC_NZ);
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MOVI2R(fullAlphaReg, 0);
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// SetJumpTarget(skip);
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}
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void VertexDecoderJitCache::Jit_TcU8() {
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LDRB(INDEX_UNSIGNED, tempReg1, srcReg, dec_->tcoff);
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LDRB(INDEX_UNSIGNED, tempReg2, srcReg, dec_->tcoff + 1);
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ORR(tempReg1, tempReg1, tempReg2, ArithOption(tempReg2, ST_LSL, 8));
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STR(INDEX_UNSIGNED, tempReg1, dstReg, dec_->decFmt.uvoff);
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}
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void VertexDecoderJitCache::Jit_TcU16() {
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LDRH(INDEX_UNSIGNED, tempReg1, srcReg, dec_->tcoff);
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LDRH(INDEX_UNSIGNED, tempReg2, srcReg, dec_->tcoff + 2);
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ORR(tempReg1, tempReg1, tempReg2, ArithOption(tempReg2, ST_LSL, 16));
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STR(INDEX_UNSIGNED, tempReg1, dstReg, dec_->decFmt.uvoff);
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}
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void VertexDecoderJitCache::Jit_TcFloat() {
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LDR(INDEX_UNSIGNED, tempReg1, srcReg, dec_->tcoff);
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LDR(INDEX_UNSIGNED, tempReg2, srcReg, dec_->tcoff + 4);
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STR(INDEX_UNSIGNED, tempReg1, dstReg, dec_->decFmt.uvoff);
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STR(INDEX_UNSIGNED, tempReg2, dstReg, dec_->decFmt.uvoff + 4);
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}
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// Just copy 12 bytes.
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void VertexDecoderJitCache::Jit_PosFloat() {
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LDR(INDEX_UNSIGNED, tempReg1, srcReg, dec_->posoff);
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LDR(INDEX_UNSIGNED, tempReg2, srcReg, dec_->posoff + 4);
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LDR(INDEX_UNSIGNED, tempReg3, srcReg, dec_->posoff + 8);
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STR(INDEX_UNSIGNED, tempReg1, dstReg, dec_->decFmt.posoff);
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STR(INDEX_UNSIGNED, tempReg2, dstReg, dec_->decFmt.posoff + 4);
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STR(INDEX_UNSIGNED, tempReg3, dstReg, dec_->decFmt.posoff + 8);
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}
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