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Add two new instructions to the MIPS interpreter for logging. vertex.pbp demo seems to use one of them.
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@ -798,6 +798,29 @@ namespace MIPSInt
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PC += 4;
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}
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void Int_Special2(MIPSOpcode op)
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{
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static int reported = 0;
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switch (op & 0x3F)
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{
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case 36:
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if (!reported) {
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Reporting::ReportMessage("MFIC instruction hit (%08x) at %08x", op, currentMIPS->pc);
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WARN_LOG(CPU,"MFIC Disable/Enable Interrupt CPU instruction");
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reported = 1;
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}
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break;
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case 38:
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if (!reported) {
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Reporting::ReportMessage("MTIC instruction hit (%08x) at %08x", op, currentMIPS->pc);
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WARN_LOG(CPU,"MTIC Disable/Enable Interrupt CPU instruction");
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reported = 1;
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}
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break;
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}
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PC += 4;
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}
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void Int_Special3(MIPSOpcode op)
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{
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int rs = _RS;
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@ -48,6 +48,7 @@ namespace MIPSInt
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void Int_FPUComp(MIPSOpcode op);
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void Int_FPUBranch(MIPSOpcode op);
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void Int_Emuhack(MIPSOpcode op);
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void Int_Special2(MIPSOpcode op);
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void Int_Special3(MIPSOpcode op);
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void Int_Interrupt(MIPSOpcode op);
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void Int_Cache(MIPSOpcode op);
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@ -257,9 +257,9 @@ const MIPSInstruction tableSpecial2[64] = // 011100 ..... ..... ..... ..... xxxx
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INVALID_X_8,
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//32
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INVALID, INVALID, INVALID, INVALID,
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INSTR("mfic", &Jit::Comp_Generic, Dis_Generic, 0, 0),
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INSTR("mfic", &Jit::Comp_Generic, Dis_Generic, Int_Special2, 0),
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INVALID,
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INSTR("mtic", &Jit::Comp_Generic, Dis_Generic, 0, 0),
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INSTR("mtic", &Jit::Comp_Generic, Dis_Generic, Int_Special2, 0),
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INVALID,
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//40
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INVALID_X_8,
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@ -366,7 +366,7 @@ void Jit::Comp_Generic(MIPSOpcode op)
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ABI_CallFunctionC((void *)func, op.encoding);
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}
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else
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ERROR_LOG_REPORT(JIT, "Trying to compile instruction that can't be interpreted");
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ERROR_LOG_REPORT(JIT, "Trying to compile instruction %08x that can't be interpreted", op.encoding);
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const MIPSInfo info = MIPSGetInfo(op);
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if ((info & IS_VFPU) != 0 && (info & VFPU_NO_PREFIX) == 0)
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