Add two new instructions to the MIPS interpreter for logging. vertex.pbp demo seems to use one of them.

This commit is contained in:
The Dax 2013-08-25 16:28:19 -04:00
parent fbfbe6d90d
commit a35a407207
4 changed files with 27 additions and 3 deletions

View File

@ -798,6 +798,29 @@ namespace MIPSInt
PC += 4;
}
void Int_Special2(MIPSOpcode op)
{
static int reported = 0;
switch (op & 0x3F)
{
case 36:
if (!reported) {
Reporting::ReportMessage("MFIC instruction hit (%08x) at %08x", op, currentMIPS->pc);
WARN_LOG(CPU,"MFIC Disable/Enable Interrupt CPU instruction");
reported = 1;
}
break;
case 38:
if (!reported) {
Reporting::ReportMessage("MTIC instruction hit (%08x) at %08x", op, currentMIPS->pc);
WARN_LOG(CPU,"MTIC Disable/Enable Interrupt CPU instruction");
reported = 1;
}
break;
}
PC += 4;
}
void Int_Special3(MIPSOpcode op)
{
int rs = _RS;

View File

@ -48,6 +48,7 @@ namespace MIPSInt
void Int_FPUComp(MIPSOpcode op);
void Int_FPUBranch(MIPSOpcode op);
void Int_Emuhack(MIPSOpcode op);
void Int_Special2(MIPSOpcode op);
void Int_Special3(MIPSOpcode op);
void Int_Interrupt(MIPSOpcode op);
void Int_Cache(MIPSOpcode op);

View File

@ -257,9 +257,9 @@ const MIPSInstruction tableSpecial2[64] = // 011100 ..... ..... ..... ..... xxxx
INVALID_X_8,
//32
INVALID, INVALID, INVALID, INVALID,
INSTR("mfic", &Jit::Comp_Generic, Dis_Generic, 0, 0),
INSTR("mfic", &Jit::Comp_Generic, Dis_Generic, Int_Special2, 0),
INVALID,
INSTR("mtic", &Jit::Comp_Generic, Dis_Generic, 0, 0),
INSTR("mtic", &Jit::Comp_Generic, Dis_Generic, Int_Special2, 0),
INVALID,
//40
INVALID_X_8,

View File

@ -366,7 +366,7 @@ void Jit::Comp_Generic(MIPSOpcode op)
ABI_CallFunctionC((void *)func, op.encoding);
}
else
ERROR_LOG_REPORT(JIT, "Trying to compile instruction that can't be interpreted");
ERROR_LOG_REPORT(JIT, "Trying to compile instruction %08x that can't be interpreted", op.encoding);
const MIPSInfo info = MIPSGetInfo(op);
if ((info & IS_VFPU) != 0 && (info & VFPU_NO_PREFIX) == 0)