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Fix old bug breaking "non-fast" memory on ARM64. May help #9477, also see #9488

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Henrik Rydgård 2017-03-23 16:52:12 +01:00
parent 1094842b55
commit a769724fd0
1 changed files with 6 additions and 3 deletions
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9
Core/MIPS/ARM64/Arm64CompLoadStore.cpp
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@ -87,14 +87,17 @@ namespace MIPSComp {
// We can do this a little smarter by shifting out the lower 8 bits, since blocks are 0x100 aligned.
// PSP_GetUserMemoryEnd() is dynamic, but the others encode to imms just fine.
// So we only need to safety check the one value.
// This is because ARM64 immediates for many instructions like CMP can only encode
// immediates up to 12 bits, shifted by 12 or not.
if ((PSP_GetUserMemoryEnd() & 0x000FFFFF) == 0) {
// In other words, shift right 8.
UBFX(tempReg, SCRATCH1, 8, 24);
// In other words, shift right 8, and kill off the top 4 bits as we don't want them involved in the ocmpares.
UBFX(tempReg, SCRATCH1, 8, 24 - 4);
// Now check if we're higher than that.
CMPI2R(tempReg, PSP_GetUserMemoryEnd() >> 8);
} else {
// Compare first using the tempReg, then shift into it.
// Compare first using the tempReg (need it because we have a full 28-bit value), then shift into it.
ANDI2R(SCRATCH1, SCRATCH1, 0x0FFFFFFF);
CMPI2R(SCRATCH1, PSP_GetUserMemoryEnd(), tempReg);
UBFX(tempReg, SCRATCH1, 8, 24);
}