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riscv: Don't cache mipState on backend.

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Bad sign if we're trying to use it, anyway.
This commit is contained in:
Unknown W. Brackets 2023-08-06 00:21:49 -07:00
parent e9431d0d1e
commit ad4cbbab8e
5 changed files with 6 additions and 8 deletions
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2
Core/MIPS/IR/IRNativeCommon.cpp
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@ -394,7 +394,7 @@ IRNativeJit::IRNativeJit(MIPSState *mipsState)
void IRNativeJit::Init(IRNativeBackend &backend) {
backend_ = &backend;
debugInterface_.Init(&backend_->CodeBlock());
backend_->GenerateFixedCode();
backend_->GenerateFixedCode(mips_);
// Wanted this to be a reference, but vtbls get in the way. Shouldn't change.
hooks_ = backend.GetNativeHooks();

2
Core/MIPS/IR/IRNativeCommon.h
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@ -56,7 +56,7 @@ public:
bool CodeInRange(const u8 *ptr) const;
int OffsetFromCodePtr(const u8 *ptr);
virtual void GenerateFixedCode() = 0;
virtual void GenerateFixedCode(MIPSState *mipsState) = 0;
virtual bool CompileBlock(IRBlock *block, int block_num, bool preload) = 0;
virtual void ClearAllBlocks() = 0;

4
Core/MIPS/RiscV/RiscVAsm.cpp
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@ -44,7 +44,7 @@ static void ShowPC(u32 downcount, void *membase, void *jitbase) {
count++;
}
void RiscVJitBackend::GenerateFixedCode() {
void RiscVJitBackend::GenerateFixedCode(MIPSState *mipsState) {
BeginWrite(GetMemoryProtectPageSize());
const u8 *start = AlignCodePage();
@ -120,7 +120,7 @@ void RiscVJitBackend::GenerateFixedCode() {
// Fixed registers, these are always kept when in Jit context.
LI(MEMBASEREG, Memory::base, SCRATCH1);
LI(CTXREG, mips_, SCRATCH1);
LI(CTXREG, mipsState, SCRATCH1);
LI(JITBASEREG, GetBasePtr(), SCRATCH1);
LoadStaticRegisters();

2
Core/MIPS/RiscV/RiscVJit.cpp
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@ -26,7 +26,7 @@ using namespace RiscVGen;
using namespace RiscVJitConstants;
RiscVJitBackend::RiscVJitBackend(MIPSState *mipsState, JitOptions &jitopt)
: mips_(mipsState), jo(jitopt), gpr(mipsState, &jo), fpr(mipsState, &jo) {
: jo(jitopt), gpr(mipsState, &jo), fpr(mipsState, &jo) {
// Automatically disable incompatible options.
if (((intptr_t)Memory::base & 0x00000000FFFFFFFFUL) != 0) {
jo.enablePointerify = false;

4
Core/MIPS/RiscV/RiscVJit.h
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@ -36,7 +36,7 @@ public:
bool DescribeCodePtr(const u8 *ptr, std::string &name) const override;
void GenerateFixedCode() override;
void GenerateFixedCode(MIPSState *mipsState) override;
bool CompileBlock(IRBlock *block, int block_num, bool preload) override;
void ClearAllBlocks() override;
@ -107,8 +107,6 @@ private:
void NormalizeSrc12(IRInst inst, RiscVGen::RiscVReg *lhs, RiscVGen::RiscVReg *rhs, RiscVGen::RiscVReg lhsTempReg, RiscVGen::RiscVReg rhsTempReg, bool allowOverlap);
RiscVGen::RiscVReg NormalizeR(IRRegIndex rs, IRRegIndex rd, RiscVGen::RiscVReg tempReg);
// TODO: Maybe just a param to GenerateFixedCode().
MIPSState *mips_;
JitOptions &jo;
RiscVRegCache gpr;
RiscVRegCacheFPU fpr;