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Merge pull request #18207 from unknownbrackets/irjit-safe-mem
irjit: Correct alignment checks against SP
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commit
ae0305d974
@ -1794,7 +1794,8 @@ bool ApplyMemoryValidation(const IRWriter &in, IRWriter &out, const IROptions &o
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bool spModified = false;
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for (IRInst inst : in.GetInstructions()) {
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IRMemoryOpInfo info = IROpMemoryAccessSize(inst.op);
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if (info.size != 0 && inst.src1 == MIPS_REG_SP) {
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// Note: we only combine word aligned accesses.
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if (info.size != 0 && inst.src1 == MIPS_REG_SP && info.size == 4) {
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if (spModified) {
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// No good, it was modified and then we did more accesses. Can't combine.
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spUpper = -1;
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@ -1805,11 +1806,6 @@ bool ApplyMemoryValidation(const IRWriter &in, IRWriter &out, const IROptions &o
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spUpper = -1;
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break;
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}
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if (info.size == 16 && (inst.constant & 0xF) != 0) {
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// Shouldn't happen, sp should always be aligned.
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spUpper = -1;
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break;
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}
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spLower = std::min(spLower, (int)inst.constant);
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spUpper = std::max(spUpper, (int)inst.constant + info.size);
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@ -1828,7 +1824,7 @@ bool ApplyMemoryValidation(const IRWriter &in, IRWriter &out, const IROptions &o
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std::map<uint64_t, uint8_t> checks;
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const auto addValidate = [&](IROp validate, uint8_t sz, const IRInst &inst, bool isStore) {
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if (inst.src1 == MIPS_REG_SP && skipSP) {
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if (inst.src1 == MIPS_REG_SP && skipSP && validate == IROp::ValidateAddress32) {
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if (!flushedSP) {
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out.Write(IROp::ValidateAddress32, 0, MIPS_REG_SP, spWrite ? 1U : 0U, spLower);
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if (spUpper > spLower + 4)
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