From b041e712def8be2d6b08c45765c44f0085271167 Mon Sep 17 00:00:00 2001
From: "Unknown W. Brackets" <checkins@unknownbrackets.org>
Date: Sun, 23 Jul 2023 17:55:07 -0700
Subject: [PATCH] riscv: Fix signed position bug in vertexjit.

---
 GPU/Common/VertexDecoderRiscV.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/GPU/Common/VertexDecoderRiscV.cpp b/GPU/Common/VertexDecoderRiscV.cpp
index df7d04e14d..3dc1cf5c97 100644
--- a/GPU/Common/VertexDecoderRiscV.cpp
+++ b/GPU/Common/VertexDecoderRiscV.cpp
@@ -867,8 +867,8 @@ void VertexDecoderJitCache::Jit_PosS16Through() {
 	LH(tempReg2, srcReg, dec_->posoff + 2);
 	// This one, Z, has to be unsigned.
 	LHU(tempReg3, srcReg, dec_->posoff + 4);
-	FCVT(FConv::S, FConv::WU, fpSrc[0], tempReg1, Round::TOZERO);
-	FCVT(FConv::S, FConv::WU, fpSrc[1], tempReg2, Round::TOZERO);
+	FCVT(FConv::S, FConv::W, fpSrc[0], tempReg1, Round::TOZERO);
+	FCVT(FConv::S, FConv::W, fpSrc[1], tempReg2, Round::TOZERO);
 	FCVT(FConv::S, FConv::WU, fpSrc[2], tempReg3, Round::TOZERO);
 	FS(32, fpSrc[0], dstReg, dec_->decFmt.posoff + 0);
 	FS(32, fpSrc[1], dstReg, dec_->decFmt.posoff + 4);