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Merge pull request #692 from unknownbrackets/jit-vfpu

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Prep work for vfpu jit
This commit is contained in:
Henrik Rydgård 2013-02-14 00:53:14 -08:00
commit b061217fc0
8 changed files with 88 additions and 40 deletions
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9
Core/MIPS/ARM/ArmCompVFPU.cpp
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@ -20,6 +20,11 @@
namespace MIPSComp
{
void Jit::Comp_VPFX(u32 op)
{
DISABLE;
}
void Jit::Comp_SVQ(u32 op)
{
DISABLE;
@ -39,4 +44,8 @@ namespace MIPSComp
DISABLE;
}
void Jit::Comp_Vmtvc(u32 op) {
DISABLE;
}
}

6
Core/MIPS/ARM/ArmJit.h
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@ -103,13 +103,15 @@ public:
void Comp_FPU3op(u32 op);
void Comp_FPU2op(u32 op);
void Comp_mxc1(u32 op);
void Comp_Mftv(u32 op);
void Comp_VDot(u32 op);
void Comp_DoNothing(u32 op);
void Comp_SV(u32 op);
void Comp_SVQ(u32 op);
void Comp_VPFX(u32 op);
void Comp_VDot(u32 op);
void Comp_Mftv(u32 op);
void Comp_Vmtvc(u32 op);
ArmJitBlockCache *GetBlockCache() { return &blocks; }

4
Core/MIPS/MIPSInt.cpp
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@ -517,8 +517,8 @@ namespace MIPSInt
switch((op>>21)&0x1f)
{
case 0: R(rt) = FI(fs); break; //mfc1
case 2: R(rt) = currentMIPS->ReadFCR(fs); break; //cfc1
case 0: if (rt != 0) R(rt) = FI(fs); break; //mfc1
case 2: if (rt != 0) R(rt) = currentMIPS->ReadFCR(fs); break; //cfc1
case 4: FI(fs) = R(rt); break; //mtc1
case 6: currentMIPS->WriteFCR(fs, R(rt)); break; //ctc1

19
Core/MIPS/MIPSIntVFPU.cpp
View File

@ -1336,15 +1336,16 @@ namespace MIPSInt
switch ((op >> 21) & 0x1f)
{
case 3: //mfv / mfvc
if (imm < 128) {
R(rt) = VI(imm);
} else if (imm < 128 + VFPU_CTRL_MAX) { //mtvc
R(rt) = currentMIPS->vfpuCtrl[imm - 128];
} else if (rt == 0 && imm == 255) {
// This appears to be used as a CPU interlock by some games. Do nothing.
} else {
//ERROR - maybe need to make this value too an "interlock" value?
_dbg_assert_msg_(CPU,0,"mfv - invalid register");
// rt = 0, imm = 255 appears to be used as a CPU interlock by some games.
if (rt != 0) {
if (imm < 128) {
R(rt) = VI(imm);
} else if (imm < 128 + VFPU_CTRL_MAX) { //mtvc
R(rt) = currentMIPS->vfpuCtrl[imm - 128];
} else {
//ERROR - maybe need to make this value too an "interlock" value?
_dbg_assert_msg_(CPU,0,"mfv - invalid register");
}
}
break;

12
Core/MIPS/MIPSTables.cpp
View File

@ -613,12 +613,12 @@ const MIPSInstruction tableVFPU4[32] = //110100 00000 xxxxx
MIPSInstruction tableVFPU5[8] = //110111 xxx
{
INSTR("vpfxs",&Jit::Comp_Generic, Dis_VPFXST, Int_VPFX, IS_VFPU),
INSTR("vpfxs",&Jit::Comp_Generic, Dis_VPFXST, Int_VPFX, IS_VFPU),
INSTR("vpfxt",&Jit::Comp_Generic, Dis_VPFXST, Int_VPFX, IS_VFPU),
INSTR("vpfxt",&Jit::Comp_Generic, Dis_VPFXST, Int_VPFX, IS_VFPU),
INSTR("vpfxd", &Jit::Comp_Generic, Dis_VPFXD, Int_VPFX, IS_VFPU),
INSTR("vpfxd", &Jit::Comp_Generic, Dis_VPFXD, Int_VPFX, IS_VFPU),
INSTR("vpfxs",&Jit::Comp_VPFX, Dis_VPFXST, Int_VPFX, IS_VFPU),
INSTR("vpfxs",&Jit::Comp_VPFX, Dis_VPFXST, Int_VPFX, IS_VFPU),
INSTR("vpfxt",&Jit::Comp_VPFX, Dis_VPFXST, Int_VPFX, IS_VFPU),
INSTR("vpfxt",&Jit::Comp_VPFX, Dis_VPFXST, Int_VPFX, IS_VFPU),
INSTR("vpfxd", &Jit::Comp_VPFX, Dis_VPFXD, Int_VPFX, IS_VFPU),
INSTR("vpfxd", &Jit::Comp_VPFX, Dis_VPFXD, Int_VPFX, IS_VFPU),
INSTR("viim.s",&Jit::Comp_Generic, Dis_Viim,Int_Viim, IS_VFPU),
INSTR("vfim.s",&Jit::Comp_Generic, Dis_Viim,Int_Viim, IS_VFPU),
};

17
Core/MIPS/x86/CompFPU.cpp
View File

@ -166,8 +166,6 @@ enum
void Jit::CompFPComp(int lhs, int rhs, u8 compare, bool allowNaN)
{
CONDITIONAL_DISABLE;
MOVSS(XMM0, fpr.R(lhs));
CMPSS(XMM0, fpr.R(rhs), compare);
MOVSS(M((void *) &currentMIPS->fpcond), XMM0);
@ -313,12 +311,15 @@ void Jit::Comp_mxc1(u32 op)
switch((op >> 21) & 0x1f)
{
case 0: // R(rt) = FI(fs); break; //mfc1
// Cross move! slightly tricky
fpr.StoreFromRegister(fs);
gpr.Lock(rt);
gpr.BindToRegister(rt, false, true);
MOV(32, gpr.R(rt), fpr.R(fs));
gpr.UnlockAll();
if (rt != 0)
{
// Cross move! slightly tricky
fpr.StoreFromRegister(fs);
gpr.Lock(rt);
gpr.BindToRegister(rt, false, true);
MOV(32, gpr.R(rt), fpr.R(fs));
gpr.UnlockAll();
}
return;
case 2: // R(rt) = currentMIPS->ReadFCR(fs); break; //cfc1

60
Core/MIPS/x86/CompVFPU.cpp
View File

@ -56,6 +56,7 @@ const u32 GC_ALIGNED16( signBitLower[4] ) = {0x80000000, 0, 0, 0};
void Jit::Comp_VPFX(u32 op)
{
CONDITIONAL_DISABLE;
int data = op & 0xFFFFF;
int regnum = (op >> 24) & 3;
switch (regnum) {
@ -142,7 +143,7 @@ void Jit::ApplyPrefixD(const u8 *vregs, u32 prefix, VectorSize sz, bool onlyWrit
static u32 GC_ALIGNED16(ssLoadStoreTemp[1]);
void Jit::Comp_SV(u32 op) {
// DISABLE;
CONDITIONAL_DISABLE;
s32 imm = (signed short)(op&0xFFFC);
int vt = ((op >> 16) & 0x1f) | ((op & 3) << 5);
@ -208,6 +209,8 @@ void Jit::Comp_SV(u32 op) {
void Jit::Comp_SVQ(u32 op)
{
CONDITIONAL_DISABLE;
int imm = (signed short)(op&0xFFFC);
int vt = (((op >> 16) & 0x1f)) | ((op&1) << 5);
int rs = _RS;
@ -329,23 +332,26 @@ void Jit::Comp_VDot(u32 op) {
}
void Jit::Comp_Mftv(u32 op) {
CONDITIONAL_DISABLE;
int imm = op & 0xFF;
int rt = _RT;
switch ((op >> 21) & 0x1f)
{
case 3: //mfv / mfvc
if (imm < 128) { //R(rt) = VI(imm);
fpr.StoreFromRegisterV(imm);
gpr.BindToRegister(rt, false, true);
MOV(32, gpr.R(rt), fpr.V(imm));
} else if (imm < 128 + VFPU_CTRL_MAX) { //mtvc
gpr.BindToRegister(rt, false, true);
MOV(32, gpr.R(rt), M(&currentMIPS->vfpuCtrl[imm - 128]));
} else if (rt == 0 && imm == 255) {
// This appears to be used as a CPU interlock by some games. Do nothing.
} else {
//ERROR - maybe need to make this value too an "interlock" value?
_dbg_assert_msg_(CPU,0,"mfv - invalid register");
// rt = 0, imm = 255 appears to be used as a CPU interlock by some games.
if (rt != 0) {
if (imm < 128) { //R(rt) = VI(imm);
fpr.StoreFromRegisterV(imm);
gpr.BindToRegister(rt, false, true);
MOV(32, gpr.R(rt), fpr.V(imm));
} else if (imm < 128 + VFPU_CTRL_MAX) { //mtvc
gpr.BindToRegister(rt, false, true);
MOV(32, gpr.R(rt), M(&currentMIPS->vfpuCtrl[imm - 128]));
} else {
//ERROR - maybe need to make this value too an "interlock" value?
_dbg_assert_msg_(CPU,0,"mfv - invalid register");
}
}
break;
@ -358,6 +364,15 @@ void Jit::Comp_Mftv(u32 op) {
} else if (imm < 128 + VFPU_CTRL_MAX) { //mtvc //currentMIPS->vfpuCtrl[imm - 128] = R(rt);
gpr.BindToRegister(rt, true, false);
MOV(32, M(&currentMIPS->vfpuCtrl[imm - 128]), gpr.R(rt));
// TODO: Optimization if rt is Imm?
if (imm - 128 == VFPU_CTRL_SPREFIX) {
js.prefixSKnown = false;
} else if (imm - 128 == VFPU_CTRL_TPREFIX) {
js.prefixTKnown = false;
} else if (imm - 128 == VFPU_CTRL_DPREFIX) {
js.prefixDKnown = false;
}
} else {
//ERROR
_dbg_assert_msg_(CPU,0,"mtv - invalid register");
@ -371,4 +386,23 @@ void Jit::Comp_Mftv(u32 op) {
}
}
void Jit::Comp_Vmtvc(u32 op) {
CONDITIONAL_DISABLE;
int vs = _VS;
int imm = op & 0xFF;
if (imm >= 128 && imm < 128 + VFPU_CTRL_MAX) {
fpr.MapRegV(vs, 0);
MOVSS(M(&currentMIPS->vfpuCtrl[imm - 128]), fpr.RX(vs));
fpr.ReleaseSpillLocks();
if (imm - 128 == VFPU_CTRL_SPREFIX) {
js.prefixSKnown = false;
} else if (imm - 128 == VFPU_CTRL_TPREFIX) {
js.prefixTKnown = false;
} else if (imm - 128 == VFPU_CTRL_DPREFIX) {
js.prefixDKnown = false;
}
}
}
}

1
Core/MIPS/x86/Jit.h
View File

@ -141,6 +141,7 @@ public:
void Comp_VPFX(u32 op);
void Comp_VDot(u32 op);
void Comp_Mftv(u32 op);
void Comp_Vmtvc(u32 op);
void Comp_DoNothing(u32 op);