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Fix armjit fpu load / store

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This commit is contained in:
Henrik Rydgard 2013-02-13 21:07:06 +01:00
parent 30318a4a4d
commit b0c160fa93
4 changed files with 24 additions and 16 deletions
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8
Common/ArmEmitter.cpp
View File

@ -657,13 +657,13 @@ void ARMXEmitter::VLDR(ARMReg Dest, ARMReg Base, u16 offset)
{
_assert_msg_(DYNA_REC, Dest >= S0 && Dest <= D31, "Passed Invalid dest register to VLDR");
_assert_msg_(DYNA_REC, Base <= R15, "Passed invalid Base register to VLDR");
_assert_msg_(DYNA_REC, (offset & 0xC003) == 0, "VLDR: Offset needs to be word aligned and small enough");
_assert_msg_(DYNA_REC, (offset & 0xC03) == 0, "VLDR: Offset needs to be word aligned and small enough");
if (offset & 0xC03) {
ERROR_LOG(DYNA_REC, "VLDR: Bad offset %08x", offset);
}
ERROR_LOG(DYNA_REC, "VLDR: s%i, r%i + %i", Dest - S0, Base, offset);
// ERROR_LOG(DYNA_REC, "VLDR: s%i, r%i + %i", Dest - S0, Base, offset);
bool single_reg = Dest < D0;
@ -685,12 +685,12 @@ void ARMXEmitter::VSTR(ARMReg Src, ARMReg Base, u16 offset)
{
_assert_msg_(DYNA_REC, Src >= S0 && Src <= D31, "Passed invalid src register to VSTR");
_assert_msg_(DYNA_REC, Base <= R15, "Passed invalid base register to VSTR");
_assert_msg_(DYNA_REC, (offset & 0xC003) == 0, "VSTR: Offset needs to be word aligned");
_assert_msg_(DYNA_REC, (offset & 0xC03) == 0, "VSTR: Offset needs to be word aligned");
if (offset & 0xC03) {
ERROR_LOG(DYNA_REC, "VSTR: Bad offset %08x", offset);
}
ERROR_LOG(DYNA_REC, "VSTR: s%i, r%i + %i", Src - S0, Base, offset);
// ERROR_LOG(DYNA_REC, "VSTR: s%i, r%i + %i", Src - S0, Base, offset);
bool single_reg = Src < D0;

29
Core/MIPS/ARM/ArmCompFPU.cpp
View File

@ -59,8 +59,7 @@ extern int logBlocks;
void Jit::Comp_FPULS(u32 op)
{
DISABLE
FlushAll();
s32 offset = (s16)(op & 0xFFFF);
int ft = _FT;
int rs = _RS;
@ -69,18 +68,28 @@ void Jit::Comp_FPULS(u32 op)
switch(op >> 26)
{
case 49: //FI(ft) = Memory::Read_U32(addr); break; //lwc1
gpr.MapReg(rs);
fpr.MapReg(ft, MAP_NOINIT | MAP_DIRTY);
ERROR_LOG(HLE, "lwc1 rs=%i offset=%i armr=%i", rs, offset, fpr.R(ft) - S0);
SetR0ToEffectiveAddress(rs, offset);
if (gpr.IsImm(rs)) {
u32 addr = (offset + gpr.GetImm(rs)) & 0x3FFFFFFF;
MOVI2R(R0, addr + (u32)Memory::base);
} else {
gpr.MapReg(rs);
SetR0ToEffectiveAddress(rs, offset);
ADD(R0, R0, R11);
}
VLDR(fpr.R(ft), R0, 0);
break;
case 57: //Memory::Write_U32(FI(ft), addr); break; //swc1
DISABLE;
fpr.MapReg(ft, 0);
gpr.MapReg(rs);
SetR0ToEffectiveAddress(rs, offset);
fpr.MapReg(ft);
if (gpr.IsImm(rs)) {
u32 addr = (offset + gpr.GetImm(rs)) & 0x3FFFFFFF;
MOVI2R(R0, addr + (u32)Memory::base);
} else {
gpr.MapReg(rs);
SetR0ToEffectiveAddress(rs, offset);
ADD(R0, R0, R11);
}
VSTR(fpr.R(ft), R0, 0);
break;
@ -100,7 +109,7 @@ void Jit::Comp_FPU2op(u32 op)
int fs = _FS;
int fd = _FD;
logBlocks = 1;
// logBlocks = 1;
switch (op & 0x3f)
{

1
Core/MIPS/ARM/ArmCompLoadStore.cpp
View File

@ -56,7 +56,6 @@
namespace MIPSComp
{
void Jit::SetR0ToEffectiveAddress(int rs, s16 offset) {
Operand2 op2;
if (offset) {

2
Core/MIPS/MIPSInt.cpp
View File

@ -495,7 +495,7 @@ namespace MIPSInt
void Int_FPULS(u32 op)
{
s32 offset = (s16)(op&0xFFFF);
int ft = ((op>>16)&0x1f);
int ft = _FT;
int rs = _RS;
u32 addr = R(rs) + offset;