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VMOV gpr->fpu, fixes
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@ -621,16 +621,18 @@ ARMReg ARMXEmitter::SubBase(ARMReg Reg)
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// NEON Specific
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void ARMXEmitter::VADD(IntegerSize Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
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{
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_assert_msg_(DYNA_REC, Vd >= Q0, "Pass invalid register to VADD(integer)");
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_assert_msg_(DYNA_REC, Vd >= D0, "Pass invalid register to VADD(integer)");
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_assert_msg_(DYNA_REC, cpu_info.bNEON, "Can't use VADD(integer) when CPU doesn't support it");
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bool register_quad = Vd >= Q0;
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// Gets encoded as a double register
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Vd = SubBase(Vd);
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Vn = SubBase(Vn);
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Vm = SubBase(Vm);
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Write32((0xF2 << 24) | ((Vd & 0x10) << 18) | (Size << 20) | ((Vn & 0xF) << 16) \
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| ((Vd & 0xF) << 12) | (0x8 << 8) | ((Vn & 0x10) << 3) | (1 << 6) \
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| ((Vd & 0xF) << 12) | (0x8 << 8) | ((Vn & 0x10) << 3) | (register_quad << 6) \
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| ((Vm & 0x10) << 2) | (Vm & 0xF));
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}
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@ -896,6 +898,17 @@ void ARMXEmitter::VMUL(ARMReg Vd, ARMReg Vn, ARMReg Vm)
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}
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}
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void ARMXEmitter::VMOV(ARMReg Dest, ARMReg Src, bool high)
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{
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_assert_msg_(DYNA_REC, Src < S0, "This VMOV doesn't support SRC other than ARM Reg");
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_assert_msg_(DYNA_REC, Dest >= D0, "This VMOV doesn't support DEST other than VFP");
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Dest = SubBase(Dest);
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Write32(NO_COND | (0xE << 24) | (high << 21) | ((Dest & 0xF) << 16) | (Src << 12) \
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| (11 << 8) | ((Dest & 0x10) << 3) | (1 << 4));
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}
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void ARMXEmitter::VMOV(ARMReg Dest, ARMReg Src)
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{
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if (Dest > R15)
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@ -511,6 +511,7 @@ public:
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void VADD(ARMReg Vd, ARMReg Vn, ARMReg Vm);
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void VSUB(ARMReg Vd, ARMReg Vn, ARMReg Vm);
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void VMUL(ARMReg Vd, ARMReg Vn, ARMReg Vm);
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void VMOV(ARMReg Dest, ARMReg Src, bool high);
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void VMOV(ARMReg Dest, ARMReg Src);
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void QuickCallFunction(ARMReg scratchreg, void *func);
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