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irjit: Properly account for delay slots in size.

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Otherwise we think blocks are 4 bytes too short, which can affect
invalidation.
This commit is contained in:
Unknown W. Brackets 2018-01-01 22:51:03 -08:00
parent 307efe7ecb
commit b11858d9a0
2 changed files with 21 additions and 1 deletions
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20
Core/MIPS/IR/IRCompBranch.cpp
View File

@ -104,6 +104,8 @@ void IRFrontend::BranchRSRTComp(MIPSOpcode op, IRComparison cc, bool likely) {
FlushAll();
ir.Write(IROp::ExitToConst, ir.AddConstant(targetAddr));
// Account for the delay slot.
js.compilerPC += 4;
js.compiling = false;
}
@ -141,6 +143,9 @@ void IRFrontend::BranchRSZeroComp(MIPSOpcode op, IRComparison cc, bool andLink,
// Taken
FlushAll();
ir.Write(IROp::ExitToConst, ir.AddConstant(targetAddr));
// Account for the delay slot.
js.compilerPC += 4;
js.compiling = false;
}
@ -206,6 +211,9 @@ void IRFrontend::BranchFPFlag(MIPSOpcode op, IRComparison cc, bool likely) {
CompileDelaySlot();
FlushAll();
ir.Write(IROp::ExitToConst, ir.AddConstant(targetAddr));
// Account for the delay slot.
js.compilerPC += 4;
js.compiling = false;
}
@ -261,6 +269,9 @@ void IRFrontend::BranchVFPUFlag(MIPSOpcode op, IRComparison cc, bool likely) {
// Taken
FlushAll();
ir.Write(IROp::ExitToConst, ir.AddConstant(targetAddr));
// Account for the delay slot.
js.compilerPC += 4;
js.compiling = false;
}
@ -314,6 +325,9 @@ void IRFrontend::Comp_Jump(MIPSOpcode op) {
FlushAll();
ir.Write(IROp::ExitToConst, ir.AddConstant(targetAddr));
// Account for the delay slot.
js.compilerPC += 4;
js.compiling = false;
}
@ -338,6 +352,9 @@ void IRFrontend::Comp_JumpReg(MIPSOpcode op) {
ir.WriteSetConstant(rd, GetCompilerPC() + 8);
CompileDelaySlot();
// Syscall (the delay slot) does FlushAll.
// Account for the delay slot itself in total bytes.
js.compilerPC += 4;
return; // Syscall (delay slot) wrote exit code.
} else if (delaySlotIsNice) {
if (andLink)
@ -371,6 +388,9 @@ void IRFrontend::Comp_JumpReg(MIPSOpcode op) {
js.downcountAmount = 0;
ir.Write(IROp::ExitToReg, 0, destReg, 0);
// Account for the delay slot.
js.compilerPC += 4;
js.compiling = false;
}

2
Core/MIPS/IR/IRFrontend.cpp
View File

@ -278,7 +278,7 @@ void IRFrontend::DoJit(u32 em_address, std::vector<IRInst> &instructions, std::v
if (logBlocks > 0 && dontLogBlocks == 0) {
char temp2[256];
NOTICE_LOG(JIT, "=============== mips %08x ===============", em_address);
for (u32 cpc = em_address; cpc != GetCompilerPC() + 4; cpc += 4) {
for (u32 cpc = em_address; cpc != GetCompilerPC(); cpc += 4) {
temp2[0] = 0;
MIPSDisAsm(Memory::Read_Opcode_JIT(cpc), cpc, temp2, true);
NOTICE_LOG(JIT, "M: %08x %s", cpc, temp2);