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Implement a few ALU ops in the x86 JIT-from-IR.

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This commit is contained in:
Henrik Rydgård 2023-08-21 14:32:41 +02:00
parent 11c40e6889
commit b67741509c
1 changed files with 41 additions and 3 deletions
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44
Core/MIPS/x86/X64IRCompALU.cpp
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@ -110,7 +110,11 @@ void X64JitBackend::CompIR_Arith(IRInst inst) {
break; break;
case IROp::Neg: case IROp::Neg:
CompIR_Generic(inst); regs_.Map(inst);
if (inst.dest != inst.src1) {
MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
}
NEG(32, regs_.R(inst.dest));
break; break;
default: default:
@ -131,8 +135,13 @@ void X64JitBackend::CompIR_Assign(IRInst inst) {
break; break;
case IROp::Ext8to32: case IROp::Ext8to32:
regs_.Map(inst);
MOVZX(32, 8, regs_.RX(inst.dest), regs_.R(inst.src1));
break;
case IROp::Ext16to32: case IROp::Ext16to32:
CompIR_Generic(inst); regs_.Map(inst);
MOVZX(32, 16, regs_.RX(inst.dest), regs_.R(inst.src1));
break; break;
default: default:
@ -229,9 +238,38 @@ void X64JitBackend::CompIR_Logic(IRInst inst) {
switch (inst.op) { switch (inst.op) {
case IROp::And: case IROp::And:
regs_.Map(inst);
if (inst.dest == inst.src1) {
AND(32, regs_.R(inst.dest), regs_.R(inst.src2));
} else if (inst.dest == inst.src2) {
AND(32, regs_.R(inst.dest), regs_.R(inst.src1));
} else {
MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
AND(32, regs_.R(inst.dest), regs_.R(inst.src2));
}
break;
case IROp::Or: case IROp::Or:
regs_.Map(inst);
if (inst.dest == inst.src1) {
OR(32, regs_.R(inst.dest), regs_.R(inst.src2));
} else if (inst.dest == inst.src2) {
OR(32, regs_.R(inst.dest), regs_.R(inst.src1));
} else {
MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
OR(32, regs_.R(inst.dest), regs_.R(inst.src2));
}
break;
case IROp::Xor: case IROp::Xor:
CompIR_Generic(inst); regs_.Map(inst);
if (inst.dest == inst.src1) {
XOR(32, regs_.R(inst.dest), regs_.R(inst.src2));
} else if (inst.dest == inst.src2) {
XOR(32, regs_.R(inst.dest), regs_.R(inst.src1));
} else {
MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
XOR(32, regs_.R(inst.dest), regs_.R(inst.src2));
}
break; break;
case IROp::AndConst: case IROp::AndConst: