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Couple more armjit-fpu instructions. Turn down logging a bit.

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This commit is contained in:
Henrik Rydgard 2013-02-11 23:39:30 +01:00
parent 69c3c91d7e
commit ba1171f15d
3 changed files with 11 additions and 13 deletions
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12
Core/MIPS/ARM/ArmCompFPU.cpp
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@ -69,7 +69,7 @@ void Jit::Comp_FPULS(u32 op)
int ft = _FT;
int rs = _RS;
// u32 addr = R(rs) + offset;
logBlocks = 1;
// logBlocks = 1;
switch(op >> 26)
{
case 49: //FI(ft) = Memory::Read_U32(addr); break; //lwc1
@ -100,10 +100,11 @@ void Jit::Comp_FPUComp(u32 op) {
void Jit::Comp_FPU2op(u32 op)
{
DISABLE
// DISABLE
int fs = _FS;
int fd = _FD;
logBlocks = 1;
switch (op & 0x3f)
{
@ -119,13 +120,13 @@ void Jit::Comp_FPU2op(u32 op)
case 4: //F(fd) = sqrtf(F(fs)); break; //sqrt
fpr.MapDirtyIn(fd, fs);
VSQRT(fpr.R(fd), fpr.R(fd));
VSQRT(fpr.R(fd), fpr.R(fs));
return;
case 6: //F(fd) = F(fs); break; //mov
fpr.MapDirtyIn(fd, fs);
VMOV(fpr.R(fd), fpr.R(fd));
VMOV(fpr.R(fd), fpr.R(fs));
break;
/*
@ -153,8 +154,7 @@ void Jit::Comp_FPU2op(u32 op)
case 36: //FsI(fd) = (int) F(fs); break; //cvt.w.s
*/
default:
Comp_Generic(op);
return;
DISABLE;
}
}

2
Core/MIPS/ARM/ArmJit.cpp
View File

@ -169,7 +169,7 @@ const u8 *Jit::DoJit(u32 em_address, ArmJitBlock *b)
js.downcountAmount += MIPSGetInstructionCycleEstimate(inst);
MIPSCompileOp(inst);
FlushAll(); ///HACKK
// FlushAll(); ///HACKK
js.compilerPC += 4;
numInstructions++;
}

10
Core/MIPS/ARM/ArmRegCacheFPU.cpp
View File

@ -62,7 +62,7 @@ ARMReg ArmRegCacheFPU::MapReg(MIPSReg mipsReg, int mapFlags) {
if (mapFlags & MAP_DIRTY) {
ar[mr[mipsReg].reg].isDirty = true;
}
INFO_LOG(HLE, "Already mapped %i to %i", mipsReg, mr[mipsReg].reg);
//INFO_LOG(HLE, "Already mapped %i to %i", mipsReg, mr[mipsReg].reg);
return (ARMReg)(mr[mipsReg].reg + S0);
}
@ -86,7 +86,7 @@ allocate:
ar[reg].mipsReg = mipsReg;
mr[mipsReg].loc = ML_ARMREG;
mr[mipsReg].reg = reg;
INFO_LOG(HLE, "Mapped %i to %i", mipsReg, mr[mipsReg].reg);
//INFO_LOG(HLE, "Mapped %i to %i", mipsReg, mr[mipsReg].reg);
return (ARMReg)(reg + S0);
}
}
@ -105,8 +105,6 @@ allocate:
}
if (bestToSpill != -1) {
INFO_LOG(HLE, "Spillin! %i", bestToSpill);
// ERROR_LOG(JIT, "Out of registers at PC %08x - spills register %i.", mips_->pc, bestToSpill);
FlushArmReg((ARMReg)(S0 + bestToSpill));
goto allocate;
}
@ -149,7 +147,7 @@ void ArmRegCacheFPU::FlushArmReg(ARMReg r) {
if (ar[reg].mipsReg != -1) {
if (ar[reg].isDirty && mr[ar[reg].mipsReg].loc == ML_ARMREG)
{
INFO_LOG(HLE, "Flushing ARM reg %i", reg);
//INFO_LOG(HLE, "Flushing ARM reg %i", reg);
emit->VSTR(r, CTXREG, GetMipsRegOffset(ar[reg].mipsReg));
}
@ -176,7 +174,7 @@ void ArmRegCacheFPU::FlushMipsReg(MIPSReg r) {
ERROR_LOG(HLE, "FlushMipsReg: MipsReg had bad ArmReg");
}
if (ar[mr[r].reg].isDirty) {
INFO_LOG(HLE, "Flushing dirty reg %i", mr[r].reg);
//INFO_LOG(HLE, "Flushing dirty reg %i", mr[r].reg);
emit->VSTR((ARMReg)(mr[r].reg + S0), CTXREG, GetMipsRegOffset(r));
ar[mr[r].reg].isDirty = false;
}