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irjit: Encode downcount directly as a constant.

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Simpler this way, now.
This commit is contained in:
Unknown W. Brackets 2018-01-03 23:32:31 -08:00
parent cffb2d61a7
commit bc541bd020
4 changed files with 12 additions and 12 deletions
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14
Core/MIPS/IR/IRCompBranch.cpp
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@ -92,7 +92,7 @@ void IRFrontend::BranchRSRTComp(MIPSOpcode op, IRComparison cc, bool likely) {
CompileDelaySlot();
int dcAmount = js.downcountAmount;
ir.Write(IROp::Downcount, 0, dcAmount & 0xFF, dcAmount >> 8);
ir.Write(IROp::Downcount, 0, ir.AddConstant(dcAmount));
js.downcountAmount = 0;
FlushAll();
@ -133,7 +133,7 @@ void IRFrontend::BranchRSZeroComp(MIPSOpcode op, IRComparison cc, bool andLink,
CompileDelaySlot();
int dcAmount = js.downcountAmount;
ir.Write(IROp::Downcount, 0, dcAmount & 0xFF, dcAmount >> 8);
ir.Write(IROp::Downcount, 0, ir.AddConstant(dcAmount));
js.downcountAmount = 0;
FlushAll();
@ -200,7 +200,7 @@ void IRFrontend::BranchFPFlag(MIPSOpcode op, IRComparison cc, bool likely) {
CompileDelaySlot();
int dcAmount = js.downcountAmount;
ir.Write(IROp::Downcount, 0, dcAmount & 0xFF, dcAmount >> 8);
ir.Write(IROp::Downcount, 0, ir.AddConstant(dcAmount));
js.downcountAmount = 0;
FlushAll();
@ -249,7 +249,7 @@ void IRFrontend::BranchVFPUFlag(MIPSOpcode op, IRComparison cc, bool likely) {
CompileDelaySlot();
int dcAmount = js.downcountAmount;
ir.Write(IROp::Downcount, 0, dcAmount & 0xFF, dcAmount >> 8);
ir.Write(IROp::Downcount, 0, ir.AddConstant(dcAmount));
js.downcountAmount = 0;
if (delaySlotIsBranch && (signed short)(delaySlotOp & 0xFFFF) != (signed short)(op & 0xFFFF) - 1)
@ -320,7 +320,7 @@ void IRFrontend::Comp_Jump(MIPSOpcode op) {
}
int dcAmount = js.downcountAmount;
ir.Write(IROp::Downcount, 0, dcAmount & 0xFF, dcAmount >> 8);
ir.Write(IROp::Downcount, 0, ir.AddConstant(dcAmount));
js.downcountAmount = 0;
FlushAll();
@ -384,7 +384,7 @@ void IRFrontend::Comp_JumpReg(MIPSOpcode op) {
}
int dcAmount = js.downcountAmount;
ir.Write(IROp::Downcount, 0, dcAmount & 0xFF, dcAmount >> 8);
ir.Write(IROp::Downcount, 0, ir.AddConstant(dcAmount));
js.downcountAmount = 0;
ir.Write(IROp::ExitToReg, 0, destReg, 0);
@ -397,7 +397,7 @@ void IRFrontend::Comp_JumpReg(MIPSOpcode op) {
void IRFrontend::Comp_Syscall(MIPSOpcode op) {
// Note: If we're in a delay slot, this is off by one compared to the interpreter.
int dcAmount = js.downcountAmount + (js.inDelaySlot ? -1 : 0);
ir.Write(IROp::Downcount, 0, dcAmount & 0xFF, dcAmount >> 8);
ir.Write(IROp::Downcount, 0, ir.AddConstant(dcAmount));
js.downcountAmount = 0;
// If not in a delay slot, we need to update PC.

6
Core/MIPS/IR/IRFrontend.cpp
View File

@ -162,7 +162,7 @@ void IRFrontend::Comp_ReplacementFunc(MIPSOpcode op) {
MIPSCompileOp(Memory::Read_Instruction(GetCompilerPC(), true), this);
} else {
ApplyRoundingMode();
ir.Write(IROp::Downcount, 0, js.downcountAmount & 0xFF, js.downcountAmount >> 8);
ir.Write(IROp::Downcount, 0, ir.AddConstant(js.downcountAmount));
ir.Write(IROp::ExitToReg, 0, MIPS_REG_RA, 0);
js.compiling = false;
}
@ -319,7 +319,7 @@ void IRFrontend::CheckBreakpoint(u32 addr) {
// TODO: In likely branches, downcount will be incorrect.
int downcountOffset = js.inDelaySlot && js.downcountAmount >= 2 ? -2 : 0;
int downcountAmount = js.downcountAmount + downcountOffset;
ir.Write(IROp::Downcount, 0, downcountAmount & 0xFF, downcountAmount >> 8);
ir.Write(IROp::Downcount, 0, ir.AddConstant(downcountAmount));
// Note that this means downcount can't be metadata on the block.
js.downcountAmount = -downcountOffset;
ir.Write(IROp::Breakpoint);
@ -342,7 +342,7 @@ void IRFrontend::CheckMemoryBreakpoint(int rs, int offset) {
downcountOffset = 0;
}
int downcountAmount = js.downcountAmount + downcountOffset;
ir.Write(IROp::Downcount, 0, downcountAmount & 0xFF, downcountAmount >> 8);
ir.Write(IROp::Downcount, 0, ir.AddConstant(downcountAmount));
// Note that this means downcount can't be metadata on the block.
js.downcountAmount = -downcountOffset;
ir.Write(IROp::MemoryCheck, 0, rs, ir.AddConstant(offset));

2
Core/MIPS/IR/IRInst.cpp
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@ -141,7 +141,7 @@ static const IRMeta irMeta[] = {
{ IROp::Vec2Pack31To16, "Vec2Pack31To16", "2V" },
{ IROp::Interpret, "Interpret", "_C" },
{ IROp::Downcount, "Downcount", "_II" },
{ IROp::Downcount, "Downcount", "_C" },
{ IROp::ExitToPC, "ExitToPC", "", IRFLAG_EXIT },
{ IROp::ExitToConst, "Exit", "C", IRFLAG_EXIT },
{ IROp::ExitToConstIfEq, "ExitIfEq", "CGG", IRFLAG_EXIT },

2
Core/MIPS/IR/IRInterpreter.cpp
View File

@ -762,7 +762,7 @@ u32 IRInterpret(MIPSState *mips, const IRInst *inst, int count) {
break;
case IROp::Downcount:
mips->downcount -= (inst->src1) | ((inst->src2) << 8);
mips->downcount -= inst->constant;
break;
case IROp::SetPC: