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arm64jit: Avoid arithmetic movs.

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ORR is the preferred encoding and may be faster on some chips.
This commit is contained in:
Unknown W. Brackets 2017-12-29 17:06:29 -08:00
parent 98ed6fab3f
commit c00044c5d8
3 changed files with 21 additions and 4 deletions
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12
Common/Arm64Emitter.cpp
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@ -3738,7 +3738,11 @@ void ARM64XEmitter::CMPI2R(ARM64Reg Rn, u64 imm, ARM64Reg scratch) {
bool ARM64XEmitter::TryADDI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm) {
u32 val;
bool shift;
if (IsImmArithmetic(imm, &val, &shift)) {
if (imm == 0) {
// Prefer MOV (ORR) instead of ADD for moves.
MOV(Rd, Rn);
return true;
} else if (IsImmArithmetic(imm, &val, &shift)) {
ADD(Rd, Rn, val, shift);
return true;
} else {
@ -3749,7 +3753,11 @@ bool ARM64XEmitter::TryADDI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm) {
bool ARM64XEmitter::TrySUBI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm) {
u32 val;
bool shift;
if (IsImmArithmetic(imm, &val, &shift)) {
if (imm == 0) {
// Prefer MOV (ORR) instead of ADD for moves.
MOV(Rd, Rn);
return true;
} else if (IsImmArithmetic(imm, &val, &shift)) {
SUB(Rd, Rn, val, shift);
return true;
} else {

11
Core/MIPS/ARM64/Arm64CompALU.cpp
View File

@ -262,7 +262,16 @@ void Arm64Jit::Comp_RType3(MIPSOpcode op) {
case 32: //R(rd) = R(rs) + R(rt); break; //add
case 33: //R(rd) = R(rs) + R(rt); break; //addu
CompType3(rd, rs, rt, &ARM64XEmitter::ADD, &ARM64XEmitter::TryADDI2R, &EvalAdd, true);
if (gpr.IsImm(rs) && gpr.GetImm(rs) == 0 && !gpr.IsImm(rt)) {
// Special case: actually a mov, avoid arithmetic.
gpr.MapDirtyIn(rd, rt);
MOV(gpr.R(rd), gpr.R(rt));
} else if (gpr.IsImm(rt) && gpr.GetImm(rt) == 0 && !gpr.IsImm(rs)) {
gpr.MapDirtyIn(rd, rs);
MOV(gpr.R(rd), gpr.R(rs));
} else {
CompType3(rd, rs, rt, &ARM64XEmitter::ADD, &ARM64XEmitter::TryADDI2R, &EvalAdd, true);
}
break;
case 34: //R(rd) = R(rs) - R(rt); break; //sub

2
Core/MIPS/ARM64/Arm64CompBranch.cpp
View File

@ -574,7 +574,7 @@ void Arm64Jit::Comp_JumpReg(MIPSOpcode op)
destReg = gpr.R(rs); // Safe because FlushAll doesn't change any regs
FlushAll();
} else {
// Delay slot - this case is very rare, might be able to free up R8.
// Delay slot - this case is very rare, might be able to free up W24.
gpr.MapReg(rs);
MOV(destReg, gpr.R(rs));
if (andLink)